Data Sheet, Revision 1
October 12, 2005
Ambassador
®
T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
1 Product Overview
The last issue of this data sheet was August 2003.
Revisions to this data sheet consist of additions to
Section 6 Ordering Information on page 96.
Modified
the description of pin DPUE in
Table 3.
Updated
Fig-
ure 21.
Optional 8-bit parallel input and/or 8-bit parallel
output for local TDM interfaces.
High-performance microprocessor interface:
— Provides access to device configuration regis-
ters and to time-slot data.
— Supports both
Motorola
®
nonmultiplexed and
Intel
®
multiplexed/nonmultiplexed modes.
Two independently programmable groups of up to
12 framing signals each.
Devices available in 0.25 micron technology.
3.3 V supply with 5 V tolerant inputs and TTL-com-
patible outputs.
Boundary-scan testing support.
208-pin, plastic SQFP package.
217-ball PBGA package (industrial temperature
range).
1.1 Features
Complete solution for interfacing board-level cir-
cuitry to the H.100/H.110 telephony bus.
H.100/H.110 compliant interface; all mandatory
signals.
Programmable connections to any of the 4096 time
slots on the H.100/H.110 bus.
Up to 16 local serial inputs and 16 local serial out-
puts, programmable for 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s operation per CHI
specifications.
Programmable switching between local time slots,
up to 1024 connections.
Subrate switching of nibbles, dibits, or bits.
Backward compatible to T810X through software.
Programmable switching between local time slots
and H.100/H.110 bus, up to 512 (T8102, T8105
only) connections.
Choice of frame integrity or minimum latency
switching on a per-time-slot basis:
— Frame integrity to ensure proper switching of
wideband data.
— Minimum latency switching to reduce delay in
voice channels.
On-chip phase-locked loop (PLL) for H.100/H.110,
MVIP, or SC-Bus clock operation in master or slave
clock modes.
Serial TDM bus rate and format conversion
between most standard buses.
1.2 Description
The
Ambassador
T810X family of products provide a
complete time-slot switch and an interface for the
H.100/H.110/H.110 time-division multiplexed (TDM)
buses. The T810X family includes devices with hier-
archical switching as well as a capacity of up to 512
local to H.100/H.110 connections. The hierarchical
switching allows up to 1024 local connections without
using H.100/H.110 bus bandwidth. The T8102 device
provides for a low-cost solution in nonhierarchical
systems.
All three TSI chips are backward compatible with the
bus standards MVIP-90 and
Dialogic's
®
SC-Bus, as
well as support the newer standards, H-MVIP and
ECTF H.100/H.110. Other features include a built-in
PLL for H.100/H.110, MVIP, or SC-Bus clock opera-
tion in master or slave clock modes and two indepen-
dently programmable groups of up to 12 framing
signals each. Packaged in both a 208-pin SQFP and
a 217-ball PBGA, the T810X TSI devices provide an
economic solution for the computer telephony mar-
ket.
Ambassador
T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Data Sheet, Revision 1
October 12, 2005
Table of Contents
Contents
Page
Contents
Page
1 Product Overview .....................................................1
1.1 Features..............................................................1
1.2 Description ..........................................................1
1.3 Pin Information....................................................6
1.4
Ambassador
TSI Architecture ...........................12
1.5 Selecting Between T8105, T8102, T8100A ......12
1.6 Enhanced Local Stream Addressing.................12
1.7 Full H.100/H.110 Stream Address Support.......12
1.8 Onboard PLLs and Clock Monitors ...................12
1.9 Phase Alignment of Referenced and
Generated Frames ............................................12
1.10 Interfaces ........................................................13
1.10.1 Microprocessors ........................................13
1.10.2 Framing Groups ........................................13
1.10.3 General-Purpose Register and I/O............13
1.11 Applications.....................................................13
1.12 Application Overview ......................................13
2 Architecture and Functional Description.................13
2.1 Register/Memory Maps.....................................15
2.1.1 Main Registers ............................................15
2.1.2 Master Control and Status Register ............15
2.1.3 Address Mode Register...............................16
2.1.4 Control Register Memory Space .................17
2.2 Local Bus Section .............................................23
2.2.1 Constant Frame Delay and Minimum
Delay Connections ......................................24
2.2.2 Serial and Parallel .......................................24
2.2.3 Data Rates and Time-Slot Allocation ..........25
2.2.4 LBS: Local Stream Control, 0x0C ...............28
2.2.5 State Counter Operation .............................29
2.2.6 Software to Reset the Local Connection
Memory .......................................................29
2.3 H-Bus Section ...................................................30
2.3.1 Memory Architecture ...................................30
2.3.2 CAM Operation and Commands .................32
2.3.3 H-Bus Access..............................................36
2.3.4 L-Bus Access ..............................................37
2.3.5 H-Bus Rate Selection and Connection
Address Format...........................................37
2.4 Subrate Switching for the
Ambassador
Family................................................................39
2.4.1 Description, Operation, and Application ......39
2.4.2 Definitions ...................................................39
2.4.3 Subrate Switching on H.100/H.110 .............39
2.4.4 Using the Existing Architecture ...................40
2.4.5 Limitations ...................................................42
2.4.6 Minimum vs. Constant Delay.......................43
2.4.7 Example of a Practical Application ..............43
2.5 Clocking Section ...............................................43
2.5.1 Clock and NETREF Selection .....................45
2
2.5.2 Dividers and Rate Multipliers...................... 45
2.5.3 State Machines........................................... 45
2.5.4 Frame Sync ................................................ 45
2.5.5 Bit Sliding (Frame Locking) ........................ 45
2.5.6 MTIE........................................................... 46
2.5.6.1 MTIE Compliance ................................. 46
2.5.6.2 Relationship of the Bit Slider to MTIE ... 46
2.5.6.3 Using the Bit Slider ............................... 46
2.5.7 Clock Fallback ............................................ 47
2.5.8 Clock Control Register Definitions.............. 49
2.5.8.1 Basic Fallback Mode............................. 54
2.5.8.2 CKMD, CKND, CKRD: Clocks, Main,
NETREF, Resource Dividers
0x07, 0x08, 0x09 .................................. 55
2.5.9 LREF Pairing .............................................. 57
2.5.9.1 LREF Port Configuration....................... 57
2.5.9.2 Operation .............................................. 58
2.5.9.3 Example of LREF Pairing on a T8100A 58
2.5.9.4 Advantages of LREF Pairing ................ 58
2.6 Interface Section .............................................. 58
2.6.1 Microprocessor Interface............................ 58
2.6.2 General-Purpose Register.......................... 58
2.6.3 Framing Groups ......................................... 59
2.6.3.1 Frame Group Timing............................. 60
2.7 Error Registers ................................................. 62
2.8 The JTAG Test Access Port............................. 64
2.8.1 Overview of the JTAG Architecture ............ 64
2.8.2 Overview of the JTAG Instructions............. 64
2.8.3 Elements of JTAG Logic............................. 65
2.9 Testing and Diagnostics................................... 66
2.9.1 Testing Operations ..................................... 66
2.9.2 Diagnostics................................................. 66
3 Using the TSI Devices ........................................... 69
3.1 Resets .............................................................. 69
3.1.1 Hardware Reset ......................................... 69
3.1.2 Software Reset........................................... 69
3.1.3 Power-On Reset......................................... 69
3.2 Device Settings ................................................ 70
3.2.1 Architecture ................................................ 70
3.3 Basic Connections ........................................... 71
3.3.1 LPUE Control Pins ..................................... 71
3.3.2 H.100/H.110 Data Pin Series
Termination ................................................ 71
3.3.3 H.110 Hot Swap ......................................... 71
3.3.4 Physical Connections for H.100 ................. 72
3.3.5 Physical Connections for H.110 ................. 72
3.3.6 PC Board PBGA Considerations................ 72
3.4 Using the LAR, AMR, and IDR for
Connections ..................................................... 73
3.4.1 Setting Up Local Connections (T8100A,
T8105 Only)................................................ 73
Agere Systems Inc.
Data Sheet, Revision 1
October 12, 2005
Ambassador
T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Table of Contents
(continued)
Contents
Page
Figures
Page
3.4.2 Setting Up H-Bus Connections....................75
3.4.3 Programming Examples ..............................78
3.4.4 Miscellaneous Commands ..........................81
4 Electrical Characteristics ........................................82
4.1 Absolute Maximum Ratings ..............................82
4.2 Handling Precautions ........................................82
4.3 Crystal Information ............................................83
4.4 Reset Pulse.......................................................83
4.5 Thermal Considerations ....................................83
4.5.1 Thermal Considerations for the 208 SQFP .83
4.5.2 Thermal Considerations for the 217 PBGA .83
4.6 dc Electrical Characteristics, H-Bus (ECTF
H.100 Spec., Rev. 1.0) ......................................84
4.6.1 Electrical Drive Specifications—CT_C8
and /CT_FRAME............................................84
4.7 dc Electrical Characteristics, All Other Pins ......84
4.8 H-Bus Timing (Extract from H.100 Spec.,
Rev. 1.0)............................................................85
4.8.1 Clock Alignment .........................................85
4.8.2 Frame Diagram ...........................................85
4.8.3 Detailed Timing Diagram.............................86
4.8.4 ac Electrical Characteristics, Timing,
H-Bus (H.100 Spec., Rev. 1.0)....................87
4.8.5 Detailed Clock Skew Diagram.....................88
4.8.6 ac Electrical Characteristics, Skew
Timing, H-Bus (H.100 Spec., Rev. 1.0) .......88
4.8.7 Reset and Power On ...................................89
4.9 ac Electrical Characteristics, Local Streams,
and Frames .......................................................89
4.10 ac Electrical Characteristics, Microprocessor
Timing .............................................................91
4.10.1 Microprocessor Access
Intel
Multiplexed
Write and Read Cycles..............................91
4.10.2 Microprocessor Access
Motorola
Write
and Read Cycles .......................................92
4.10.3 Microprocessor Access
Intel
Demultiplexed
Write and Read Cycles..............................93
5 Outline Diagrams....................................................94
5.1 208-Pin Square Quad Flat Package (SQFP) ....94
5.2 217-Ball Plastic Ball Grid Array (PBGA) ...........95
6 Ordering Information...............................................96
Appendix A. Application of Clock Modes...................97
Appendix B. Minimum Delay and Constant
Delay Connections ..............................103
B.1 Connection Definitions....................................103
B.2 Delay Type Definitions....................................104
B.2.1 Exceptions to Minimum Delay...................105
B.2.2 Lower Stream Rates .................................105
B.2.3 Mixed Minimum/Constant Delay ...............106
Appendix C. CAM Readback and Pattern
Fill Mode .............................................107
Agere Systems Inc.
Figure 1. 208 SQFP—Top View ................................. 6
Figure 2. 217 PBGA—Top View ................................. 7
Figure 3. Block Diagram of the TSI Devices............. 14
Figure 4. Local Bus Section Function ....................... 23
Figure 5. Local Bus Memory Connection Modes...... 24
Figure 6. Local Streams, Memory Structure ............. 25
Figure 7. Local Memory (T8100A, T8105 Only),
Fill Patterns ............................................... 26
Figure 8. Simplified Local Memory State
Timing, 65.536 MHz Clock ........................ 29
Figure 9. CAM Architecture ...................................... 31
Figure 10. Simplified H-Bus State Timing,
65.536 MHz Clock ................................... 33
Figure 11. Illustration of CAM Cycles ....................... 35
Figure 12. Subrate Switching Example .................... 39
Figure 13. Modifications for Subrate Switching ........ 41
Figure 14. Unpacking Example Using Local
Loopback ................................................. 42
Figure 15. Constant Delay/Minimum Delay
Example .................................................. 43
Figure 16. Clocking Section...................................... 44
Figure 17. A, B, and C Clock Fallback State
Diagram ................................................... 47
Figure 18. Programming Sequence.......................... 48
Figure 19. Frame Group Output Options .................. 61
Figure 20. External Connection to PLLs ................... 71
Figure 21. Physical Connections for H.110 .............. 72
Figure 22. Local-to-Local Connection
Programming (T8100A, T8105 Only) ...... 74
Figure 23. CAM Programming, H-Bus-to-Local
Connection .............................................. 76
Figure 24. Clock Alignment ...................................... 85
Figure 25. Frame Diagram ....................................... 85
Figure 26. Detailed Timing Diagram ......................... 86
Figure 27. Detailed Clock Skew Diagram ................. 88
Figure 28. ac Electrical Characteristics,
Local Streams, and Frames .................... 90
Figure 29. Microprocessor Access
Intel
Multiplexed Write Cycle ........................... 91
Figure 30. Microprocessor Access
Intel
Multiplexed Read Cycle........................... 91
Figure 31. Microprocessor Access
Motorola
Write Cycle .............................................. 92
Figure 32. Microprocessor Access
Motorola
Read Cycle .............................................. 92
Figure 33. Microprocessor Access
Intel
Demultiplexed Write Cycle ...................... 93
Figure 34. Microprocessor Access
Intel
Demultiplexed Read Cycle ...................... 93
3
Ambassador
T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Data Sheet, Revision 1
October 12, 2005
Table of Contents
(continued)
Figures
Page
Tables
Page
Figure 35. E1, CT Bus Master, Compatibility
Clock Master, Clock Source = 2.048 MHz
from Trunk ................................................98
Figure 36. T1, CT Bus Master, Compatibility
Clock Master, Clock Source = 1.544 MHz
from Trunk ................................................99
Figure 37. E1, Slave to CT Bus, Clock Source
Is Either a 16 MHz or a 4 MHz or a 2 MHz
and Frame, NETREF Source = 2.048 MHz
from Trunk ..............................................100
Figure 38. T1, Slave to CT Bus, Clock Source
Is Either a 16 MHz or a 4 MHz or a 2 MHz
and Frame, NETREF Source = 1.544 MHz
from Trunk ..............................................101
Figure 39. Constant Delay Connections,
CON[1:0] = 0X ........................................104
Figure 40. Minimum Delay Connections,
CON[1:0] = 0X ........................................105
Figure 41. Mixed Minimum/Constant Delay
Connections, CON[1:0 = 10] ..................106
Figure 42. Extended Linear (Mixed Minimum/Constant)
Delay, CON[1:0] = 11 .............................107
Figure 43. CAM Fill Patterns ...................................108
Tables
Page
Table 1. Pin Descriptions: Clocking and Framing
Pins ...............................................................8
Table 2. Pin Descriptions: Local Streams Pins ............9
Table 3. Pin Descriptions: H-Bus Pins .........................9
Table 4. Pin Descriptions: Microprocessor Interface
Pins .............................................................10
Table 5. Pin Descriptions: JTAG Pins .......................10
Table 6. Pin Descriptions: Power Pins ......................11
Table 7. Pin Descriptions: Other Pins .......................11
Table 8. Addresses of Programming Registers ..........15
Table 9. Master Control and Status Register ............15
Table 10. Address Mode Register ..............................16
Table 11. Control Register Memory Space ................17
Table 12. CKM: Clocks, Main Clock Selection,
0x00 ..........................................................18
Table 13. CKN: Clocks, NETREF Selections,
0x01 ..........................................................18
Table 14. CKP: Clocks, Programmable Outputs,
0x02 ..........................................................18
Table 15. CKR: Clocks, Resource Selection,
0x03 ..........................................................18
Table 16. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ........................................ 18
Table 17. CK32: Clocks, Locals 3 and 2, 0x05 ........ 18
Table 18. CK10: Clocks, Locals 1 and 0, 0x06 ........ 18
Table 19. CKMD: Clocks, Main Divider; CKND:
Clocks, NETREF Divider; CKRD: Clocks,
Resource Divider, 0x07, 0x08, 0x09 ........ 19
Table 20. LBS: Local Stream Control, 0x0C ............ 19
Table 21. CON: Connection Delay Type, 0x0E ........ 19
Table 22. HSL: H-Bus Stream Control, Low Byte,
0x10 ......................................................... 19
Table 23. HSH: H-Bus Stream Control, High Byte,
0x11 ......................................................... 19
Table 24. GPD, General-Purpose Direction Control
Register, 0x17 ............................................ 19
Table 25. GPR: General-Purpose I/O Register,
0x18 ......................................................... 20
Table 26. FRLA: Frame Group A, Start Address
Low, 0x20 ................................................. 20
Table 27. FRHA: Frame Group A, High Address and
Control, 0x21 ............................................ 20
Table 28. FRLB: Frame Group B, Start Address
Low, 0x22 ................................................. 20
Table 29. FRHB: Frame Group B, High Address
and Control, 0x23 ..................................... 20
Table 30. FRPL: Frame Group B, Programmed
Output, Low, 0x24 .................................... 21
Table 31. FRPH: Frame Group B, Programmed
Output, High, 0x25 ................................... 21
Table 32. CLKERR1: Clock Error Register, Error
Indicator, 0x28 ......................................... 21
Table 33. CLKERR2: Clock Error Register, Current
Status, 0x29 ............................................. 21
Table 34. SYSERR: System Error Register,
0x2A ......................................................... 21
Table 35. CKW: Clock Error/Watchdog Masking
Register, 0x2B ......................................... 21
Table 36. CLKERR3: Clock Error Register, Current
Status, 0x2C............................................... 21
Table 37. DIAG1: Diagnostics Register 1, 0x30 ....... 22
Table 38. DIAG2: Diagnostics Register 2, 0x31 ....... 22
Table 39. DIAG3: Diagnostics Register 3, 0x32 ....... 22
Table 40.
DEV_ID: Device Identification Register,
0xFE
.......................................................... 22
Table 41.
GMODE: Global Mode Register, 0xFF...... 22
Table 42. LBS: Local Stream Control, 0x0C ............ 28
4
Agere Systems Inc.
Data Sheet, Revision 1
October 12, 2005
Ambassador
T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Tables
Page
Page
Table of Contents
(continued)
Tables
Table 43. HSL:
H-Bus Stream Control, Low Byte,
0x10
............................................................37
Table 44. HSL:
H-Bus Stream Control, High Byte,
0x11
............................................................38
Table 45. Permitted Tag Extensions ..........................40
Table 46. CKM: Clocks, Main Clock Selection,
0x00 ...........................................................49
Table 47. CKN: Clocks, NETREF Selections,
0x01 ...........................................................50
Table 48. CKP: Clocks, Programmable Outputs,
0x02 ...........................................................51
Table 49. CKR: Clocks, Resource Selection,
0x03 ...........................................................52
Table 50. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ..........................................53
Table 51. CK32 and CK10: Clocks, Locals 3, 2, 1,
and 0, 0x05 and 0x06 ................................55
Table 52. CON Register 0x0E ....................................56
Table 53. LREF Pairs..................................................57
Table 54.
CKM (0x00) CKSEL Values to Select
LREF Pairs .................................................57
Table 55. FRHA, Frame Group A High Address
and Control, 0x21 .....................................59
Table 56. FRHB, Frame Group B High Address
and Control, 0x23 ......................................59
Table 57. FRPH: Frame Group B, Programmed
Output, High, 0x25 ....................................61
Table 58. CLKERR1 and CLKERR2: Error Indicator
and Current Status, 0x28 and 0x29 ...........62
Table 59. CLKERR3: Error Indicator and Current
Status, 0x2C .............................................63
Table 60. SYSERR: System Error Register,
0x2A ..........................................................63
Table 61. JTAG Instruction Set .................................64
Table 62. JTAG Scan Register .................................65
Table 63. DIAG1: Diagnostics Register 1, 0x30..........67
Table 64. DIAG2: Diagnostics Register 2, 0x31..........68
Table 65. DIAG3: Diagnostics Register 3, 0x32..........68
Table 66. Device Identification Register, 0xFE ...........70
Table 67. GMODE:
Global Mode Register, 0xFF
.......70
Table 68. LPUE Control Pins ......................................71
Table 69. Time-Slot Bit Decoding ..............................73
Table 70. IDR: Indirect Data Register, Local
Connections Only ......................................74
Table 71. IDR: Indirect Data Register, H-Bus
Connections Only .....................................75
Table 72. Crystal Specifications .................................83
Table 73.
Use of an Oscillator as an Alternative to
Using a Crystal
..........................................83
Table 74. Electrical Drive Specifications—CT_C8
and /CT_FRAME .......................................84
Table 75. dc Electrical Characteristics, All
Other Pins ..................................................84
Table 76. ac Electrical Characteristics, Timing,
H-Bus (H.100 Spec., Rev. 1.0) .................87
Table 77. ac Electrical Characteristics, Skew
Timing, H-Bus (H.100 Spec., Rev. 1.0) ....88
Table 78. Reset and Power On ..................................89
Table 79. ac Electrical Characteristics, Local
Streams, and Frames ................................89
Table 80. L_SC[3:0] and Frame Group Rise and
Fall Time .....................................................89
Table 81. Microprocessor Access Timing ..................93
Table 82. Clock Register Programming Profile for
the Four Previous Examples ...................102
Table 83. Table of Special Cases (Exceptions) .......105
Agere Systems Inc.
5
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