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T-7630---TL-DB: 产品描述DATACOM, FRAMER, PQFP144, TQFP-144; 产品类别无线/射频/通信电信电路; 文件大小3MB，共210页; 制造商AVAGO; 官网地址http://www.avagotech.com/

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T-7630---TL-DB概述

DATACOM, FRAMER, PQFP144, TQFP-144

T-7630---TL-DB规格参数

参数名称	属性值
包装说明	LFQFP,
Reach Compliance Code	unknown
JESD-30 代码	S-PQFP-G144
JESD-609代码	e0
长度	20 mm
功能数量	1
端子数量	144
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	225
认证状态	Not Qualified
座面最大高度	1.6 mm
标称供电电压	5 V
表面贴装	YES
技术	CMOS
电信集成电路类型	FRAMER
温度等级	INDUSTRIAL
端子面层	TIN LEAD
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	20 mm
Base Number Matches	1

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Preliminary Data Sheet

May 2002

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Features

The T7630 Dual T1/E1 Terminator consists of two

independent, highly integrated, software-config-

urable, full-featured short-haul transceiver/framers.

The T7630 provides glueless interconnection from a

T1/E1 line to a digital PCM system. Minimal external

clocks are needed. Only a system clock/frame sync

and a phase-locked line rate clock are required. Sys-

tem diagnostic and performance monitoring capabil-

ity with integrated programmable test pattern

generator/detector and loopback modes is provided.

Alarm reporting and performance monitoring per

AT&T

ANSI

, and ITU-T standards.

Programmable, independent transmit and receive

system interfaces at a 2.048 MHz, 4.096 MHz, or

8.192 MHz data rate.

System interface master mode for generation of

system frame sync from the line source.

Internal phase-locked loop (with external VCXO)

for generation of system clock from the line source.

Facility Data Link Features

Power Requirements and Package

Single 5 V ± 5% supply.

Low power: 375 mW per channel maximum.

144-pin TQFP package.

Operating temperature range: –40 °C to +85 °C.

HDLC or transparent modes.

Automatic transmission and detection of

ANSI

T1.403 FDL performance report message and bit-

oriented codes.

64-byte FIFO in both transmit and receive direc-

tions.

Microprocessor Interface

T1/E1 Line Interface Features

Full T1/E1 pulse template compliance.

Receiver provides equalization for up to 11 dB of

loss.

Digital clock and data recovery.

Line coding: B8ZS, HDB3, ZCS, and AMI.

Line interface coupling and matching networks for

T1 and E1 (120

Ω

and 75

Ω).

33 MHz, 8-bit data interface, no wait-states.

Intel

Motorola

interface modes with multi-

plexed or demultiplexed buses.

Directly addressable control registers.

Applications

T1/E1 Framer Features

Supports T1 framing modes ESF, D4,

SLC

-96,

T1DM DDS.

Supports G.704 basic and CRC-4 multiframe for-

mat E1 framing and procedures consistent with

G.706.

Supports unframed transmission format.

T1 signaling modes: transparent; ESF 2-state,

4-state, and 16-state; D4 2-state and 4-state;

SLC

-96 2-state, 4-state, 9-state and 16-state. E1

signaling modes: transparent and CAS.

Customer Premises Equipment—CSU/DSU,

routers, digital PBX, channel banks (CB), base

transceiver stations (BTS-picocell), small switches,

and digital subscriber loop access multiplexers

(DSLAM).

Loop/Access—DLC/IDLC,

DCS, BTS (microcell/

macrocell), DSLAMs, and multiplexers (terminal,

synchronous/asynchronous, add drop).

Central Office—Digital

switches, DCS, CB,

access concentrators, remote switch modules

(RSM), and DSLAMs.

Test Equipment—Transmission/BERT

tester.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Preliminary Data Sheet

May 2002

Table of Contents

Contents

Page

Features ................................................................................................................................................................... 1

T1/E1 Line Interface Features............................................................................................................................... 1

Power Requirements and Package....................................................................................................................... 1

T1/E1 Framer Features ......................................................................................................................................... 1

Facility Data Link Features.................................................................................................................................... 1

Microprocessor Interface....................................................................................................................................... 1

Applications ........................................................................................................................................................... 1

Feature Descriptions .............................................................................................................................................. 12

T1/E1 Line Interface Features............................................................................................................................. 12

T1/E1 Framer Features ....................................................................................................................................... 12

Facility Data Link Features.................................................................................................................................. 13

User-Programmable Microprocessor Interface ................................................................................................... 13

Functional Description ............................................................................................................................................ 14

Pin Information ....................................................................................................................................................... 18

Line Interface Unit: Block Diagram ......................................................................................................................... 25

Line Interface Unit: Receive ................................................................................................................................... 25

Data Recovery..................................................................................................................................................... 25

Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator .............................................................. 26

Receive Line Interface Configuration Modes ...................................................................................................... 26

Line Interface Unit: Transmit .................................................................................................................................. 32

Output Pulse Generation..................................................................................................................................... 32

LIU Transmitter Configuration Modes ................................................................................................................. 33

LIU Transmitter Alarms ....................................................................................................................................... 33

DSX-1 Transmitter Pulse Template and Specifications ...................................................................................... 34

CEPT Transmitter Pulse Template and Specifications ....................................................................................... 36

Line Interface Unit: Jitter Attenuator ....................................................................................................................... 37

Generated (Intrinsic) Jitter................................................................................................................................... 37

Jitter Transfer Function ....................................................................................................................................... 37

Jitter Accommodation.......................................................................................................................................... 38

Jitter Attenuator Enable (Transmit or Receive Path)........................................................................................... 38

Line Interface Unit: Loopbacks ............................................................................................................................... 41

Full Local Loopback (FLLOOP)........................................................................................................................... 41

Remote Loopback (RLOOP) ............................................................................................................................... 41

Digital Local Loopback (DLLOOP) ...................................................................................................................... 41

Line Interface Unit: Other Features ........................................................................................................................ 41

LIU Powerdown (PWRDN) .................................................................................................................................. 41

Loss of Framer Receive Line Clock (LOFRMRLCK Pin)..................................................................................... 41

In-Circuit Testing and Driver High-Impedance State (3-STATE)......................................................................... 41

LIU Delay Values................................................................................................................................................. 42

SYSCK Reference Clock........................................................................................................................................ 42

Line Interface Unit: Line Interface Networks........................................................................................................... 43

LIU-Framer Interface .............................................................................................................................................. 46

LIU-Framer Physical Interface............................................................................................................................. 46

Interface Mode and Line Encoding...................................................................................................................... 47

DS1: Alternate Mark Inversion (AMI)................................................................................................................... 48

DS1: Zero Code Suppression (ZCS)................................................................................................................... 48

CEPT: High-Density Bipolar of Order 3 (HDB3).................................................................................................. 49

Frame Formats ....................................................................................................................................................... 49

T1 Framing Structures......................................................................................................................................... 49

Agere Systems Inc.

Preliminary Data Sheet

May 2002

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Table of Contents

(continued)

Contents

Page

T1 Loss of Frame Alignment (LFA)......................................................................................................................57

T1 Frame Recovery Alignment Algorithms ..........................................................................................................58

T1 Robbed-Bit Signaling ..................................................................................................................................... 59

CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures ....................61

CEPT 2.048 Basic Frame Structure.....................................................................................................................62

CEPT Loss of Basic Frame Alignment (LFA).......................................................................................................63

CEPT Loss of Frame Alignment Recovery Algorithm ..........................................................................................63

CEPT Time Slot 0 CRC-4 Multiframe Structure...................................................................................................64

CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA) ....................................................................................65

CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms......................................................................66

CEPT Time Slot 16 Multiframe Structure.............................................................................................................70

CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA) .........................................................................71

CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm ..............................................................71

CEPT Time Slot 0 FAS/NOT FAS Control Bits ......................................................................................................71

FAS/NOT FAS Si- and E-Bit Source....................................................................................................................71

NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources ......................................................................................72

NOT FAS Sa-Bit Sources ....................................................................................................................................72

Sa Facility Data Link Access................................................................................................................................73

NOT FAS Sa Stack Source and Destination........................................................................................................74

CEPT Time Slot 16 X0—X2 Control Bits .............................................................................................................76

Signaling Access.....................................................................................................................................................76

Transparent Signaling..........................................................................................................................................76

DS1: Robbed-Bit Signaling ..................................................................................................................................76

CEPT: Time Slot 16 Signaling.................................................................................................................................77

Auxiliary Framer I/O Timing ....................................................................................................................................78

Alarms and Performance Monitoring.......................................................................................................................81

Interrupt Generation.............................................................................................................................................81

Alarm Definition....................................................................................................................................................81

Event Counters Definition ....................................................................................................................................86

Loopback and Transmission Modes ....................................................................................................................88

Line Test Patterns................................................................................................................................................91

Automatic and On-Demand Commands ..............................................................................................................95

Receive Facility Data Link Interface.....................................................................................................................97

Transmit Facility Data Link Interface..................................................................................................................103

HDLC Operation ................................................................................................................................................104

Transparent Mode..............................................................................................................................................107

Diagnostic Modes ..............................................................................................................................................108

Phase-Lock Loop Circuit .......................................................................................................................................110

Framer-System (CHI) Interface .............................................................................................................................112

DS1 Modes ........................................................................................................................................................112

CEPT Modes......................................................................................................................................................112

Receive Elastic Store.........................................................................................................................................112

Transmit Elastic Store........................................................................................................................................112

Concentration Highway Interface ..........................................................................................................................112

CHI Parameters .................................................................................................................................................113

CHI Frame Timing..............................................................................................................................................115

CHI Offset Programming....................................................................................................................................118

JTAG Boundary-Scan Specification ......................................................................................................................120

Principle of the Boundary Scan..........................................................................................................................120

Agere Systems Inc.

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Preliminary Data Sheet

May 2002

Table of Contents

(continued)

Contents

Page

Test Access Port Controller............................................................................................................................... 121

Instruction Register ........................................................................................................................................... 123

Boundary-Scan Register ................................................................................................................................... 124

BYPASS Register.............................................................................................................................................. 124

IDCODE Register .............................................................................................................................................. 124

3-State Procedures ........................................................................................................................................... 124

Microprocessor Interface ...................................................................................................................................... 125

Overview ........................................................................................................................................................... 125

Microprocessor Configuration Modes................................................................................................................ 125

Microprocessor Interface Pinout Definitions...................................................................................................... 126

Microprocessor Clock (MPCLK) Specifications................................................................................................. 127

Microprocessor Interface Register Address Map .............................................................................................. 127

I/O Timing.......................................................................................................................................................... 127

Reset .................................................................................................................................................................... 134

Hardware Reset (Pin 43/139)............................................................................................................................ 134

Software Reset/Software Restart ...................................................................................................................... 134

Register Architecture ............................................................................................................................................ 135

Global Register Architecture................................................................................................................................. 139

Global Register Structure ..................................................................................................................................... 140

Primary Block Interrupt Status Register (GREG0) ............................................................................................ 140

Primary Block Interrupt Enable Register (GREG1) ........................................................................................... 140

Global Loopback Control Register (GREG2) .................................................................................................... 141

Global Loopback Control Register (GREG3) .................................................................................................... 141

Global Control Register (GREG4) ..................................................................................................................... 142

Device ID and Version Registers (GREG5—GREG7) ...................................................................................... 142

Line Interface Unit (LIU) Register Architecture..................................................................................................... 143

Line Interface Alarm Register ............................................................................................................................... 144

Alarm Status Register (LIU_REG0)................................................................................................................... 144

Line Interface Alarm Interrupt Enable Register .................................................................................................... 144

Alarm Interrupt Enable Register (LIU_REG1) ................................................................................................... 144

Line Interface Control Registers ........................................................................................................................... 145

LIU Control Register (LIU_REG2) ..................................................................................................................... 145

LIU Control Register (LIU_REG3) ..................................................................................................................... 145

LIU Control Register (LIU_REG4) ..................................................................................................................... 146

LIU Configuration Register (LIU_REG5) ........................................................................................................... 147

LIU Configuration Register (LIU_REG6) ........................................................................................................... 147

Framer Register Architecture ............................................................................................................................... 148

Framer Status/Counter Registers...................................................................................................................... 149

FDL Register Architecture .................................................................................................................................... 190

FDL Parameter/Control Registers (800—80E; E00—E0E) .................................................................................. 191

Register Maps ...................................................................................................................................................... 198

Global Registers................................................................................................................................................ 198

Line Interface Unit Parameter/Control and Status Registers ............................................................................ 198

Framer Parameter/Control Registers (Read-Write)........................................................................................... 199

Receive Framer Signaling Registers (Read-Only) ............................................................................................ 201

Framer Unit Parameter Register Map .............................................................................................................. 202

Transmit Signaling Registers (Read/Write) ....................................................................................................... 205

Facility Data Link Parameter/Control and Status Registers (Read-Write)........................................................ 206

Absolute Maximum Ratings................................................................................................................................. 207

Agere Systems Inc.

Preliminary Data Sheet

May 2002

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Table of Contents

(continued)

Contents

Page

Operating Conditions ........................................................................................................................................... 207

Handling Precautions ............................................................................................................................................207

Electrical Characteristics .......................................................................................................................................208

Logic Interface Characteristics...........................................................................................................................208

Power Supply Bypassing ......................................................................................................................................208

Outline Diagram ....................................................................................................................................................209

144-Pin TQFP ....................................................................................................................................................209

Ordering Information .............................................................................................................................................210

Figures

Page

Figure 1. T7630 Block Diagram (One of Two Channels) ........................................................................................14

Figure 2. T7630 Block Diagram: Receive Section (One of Two Channels) ............................................................16

Figure 3. T7630 Block Diagram: Transmit Section (One of Two Channels)............................................................17

Figure 4. Pin Assignment ........................................................................................................................................18

Figure 5. Block Diagram of Line Interface Unit: Single Channel .............................................................................25

Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator ..........................................................30

Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator .......................................................................30

Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator........................................................31

Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ....................................................................31

Figure 10. DSX-1 Isolated Pulse Template .............................................................................................................34

Figure 11. ITU-T G.703 Pulse Template..................................................................................................................36

Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator ..............................................................39

Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator .......................................................................................39

Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator............................................................40

Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator.....................................................................................40

Figure 16. Line Termination Circuitry ......................................................................................................................43

Figure 17. T7630 Line Interface Unit Approximate Equivalent Analog I/O Circuits.................................................45

Figure 18. Block Diagram of Framer Line Interface ................................................................................................46

Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing.......................47

Figure 20. T1 Frame Structure ................................................................................................................................50

Figure 21. T1 Transparent Frame Structure............................................................................................................51

Figure 22. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections .......................53

Figure 23. Fs Pattern

SLC-96

Superframe Format .................................................................................................53

Figure 24. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe

Structures .............................................................................................................................................................61

Figure 25. CEPT Transparent Frame Structure ......................................................................................................62

Figure 26. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer....................................67

Figure 27. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4

Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991) ...................................69

Figure 28. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode ....73

Figure 29. Transmit and Receive Sa Stack Accessing Protocol .............................................................................75

Figure 30. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode ..............................................78

Figure 31. Timing Specification for TFS, TLCK, and TPD in DS1 Mode.................................................................78

Figure 32. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode ...........................................79

Figure 33. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode .............................79

Figure 34. Timing Specification for RCRCMFS in CEPT Mode ..............................................................................80

Figure 35. Timing Specification for TFS, TLCK, and TPD in CEPT Mode ..............................................................80

Figure 36. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode.................................................80

Figure 37. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode...........................................81

Agere Systems Inc.

T-7630---TL-DB相似产品对比

	T-7630---TL-DB
描述	DATACOM, FRAMER, PQFP144, TQFP-144
包装说明	LFQFP,
Reach Compliance Code	unknown
JESD-30 代码	S-PQFP-G144
JESD-609代码	e0
长度	20 mm
功能数量	1
端子数量	144
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	225
认证状态	Not Qualified
座面最大高度	1.6 mm
标称供电电压	5 V
表面贴装	YES
技术	CMOS
电信集成电路类型	FRAMER
温度等级	INDUSTRIAL
端子面层	TIN LEAD
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	20 mm
Base Number Matches	1

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