• 32-bit Standard Footprint supports densities from
16K x 32 through 2M x 32
• High-speed SRAMs
— Access time of 12 ns
• Low active power
— 1.650W (max.) at 12 ns
• 72 pins
• Available in ZIP, SIMM format
module is constructed from four 512K x 8 SRAMs in SOJ pack-
ages mounted on an epoxy laminate substrate. Four chip se-
lects are used to independently enable the four bytes. Reading
or writing can be executed on individual bytes or any combina-
tion of multiple bytes through proper use of selects.
The CYM1846V33 is designed for use with standard 72-pin
SIMM sockets. The pinout is downward compatible with the
64-pin JEDEC ZIP/SIMM module family (CYM1821,
CYM1831, CYM1836, and CYM1841). Thus, a single mother-
board design can be used to accommodate memory depth
ranging from 16K words (CYM1821) to 1,024K words
(CYM1851). The CYM1846V33 is offered in vertical SIMM
configuration and is available with either tin-lead or 10
micro-inches of gold flash on the edge contacts.
Presence detect pins (PD
0
−PD
3
) are used to identify module
memory density in applications where modules with alternate
word depths can be interchanged.
Functional Description
The CYM1846V33 is a high-performance 3.3V 16-megabit
static RAM module organized as 512K words by 32 bits. This
Logic Block Diagram
PD
0
-
PD
1
-
PD
2
-
PD
3
-
OPEN
OPEN
GND
OPEN
Pin Configuration
ZIP/SIMM
Top View
A
0
–A
18
OE
WE
19
512K x 8
SRAM
CS
1
512K x 8
SRAM
CS
2
512K x 8
SRAM
CS
3
512K x 8
SRAM
CS
4
I/O
0
–I/O
7
8
I/O
7
–I/O
15
8
8
I/O
16
–I/O
23
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
A
18
NC
8
I/O
24
–I/O
31
Cypress Semiconductor Corporation
Document #: 38-05275 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 15, 2002
PRELIMINARY
Selection Guide
1846V33-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Shaded area contains advance information.
CYM1846V33
1846V33-15
15
800
120
1846V33-20
20
780
120
1846V33-25
25
780
120
1846V33-35
35
780
120
12
820
120
Maximum Ratings
[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –55°C to +125°C
Ambient Temperature with
Power Applied............................................... –10°C to +85°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State ................................................ –0.5V to +V
CC
DC Input Voltage ............................................–0.5V to +4.6V
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
3.3V
+
10%
/ –5%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
CS
N
< V
IL,
F
=
F
MAX
−12
−15
−20,−25,−35
I
SB1
Automatic CS Power-Down
Current
[2]
Max. V
CC
, CS > V
IH
,
Min. Duty Cycle = 100%
–12
−15
−20,−25,−35
I
SB2
Automatic CS Power-Down
Current
[2]
Max. V
CC
, CS > V
CC
−
0.2V, V
IN
> V
CC
−
0.2V,
or V
IN
< 0.2V
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 4.0 mA
2.0
–0.3
–10
–10
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+10
+10
820
800
780
180
160
140
120
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
Shaded area contains advance information.
Capacitance
[3]
Parameter
C
INA
C
INB
C
OUT
Description
Input Capacitance (WE, OE, A
0–18
)
Input Capacitance (CS)
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
32
8
8
Unit
pF
pF
pF
Notes:
1. If device is operated at these settings, long term reliability will be affected.
2. A pull-up resistor to V
CC
on the CS input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
3. Tested on a sample basis.
Document #: 38-05275 Rev. **
Page 2 of 8
PRELIMINARY
AC Test Loads and Waveforms
R1 315
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
351
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
351
Ω
R1 315
Ω
3.0V
90%
GND
10%
CYM1846V33
ALL INPUT PULSES
90%
10%
≤
5 ns
≤
5 ns
(a)
(b)
(c)
Equivalent to:
OUTPUT
THÉVENIN
167
Ω
EQUIVALENT
1.73V
Switching Characteristics
Over the Operating Range
[4]
1846V33-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
WRITE CYCLE
[7]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[6]
12
9
9
0
1
10
7
1
3
0
7
15
10
10
0
1
12
8
1
3
0
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
[5]
CS HIGH to High Z
[5, 6]
CS HIGH to Power-Down
3
7
12
0
7
3
8
15
3
12
7
0
8
12
12
3
15
8
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1846V33-15
Min.
Max.
Unit
Shaded area contains advance information.
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. At any given temperature and voltage condition, t
HZCS
is less than t
LZCS
for any given device. These parameters are guaranteed and not 100% tested.
6. t
HZCS
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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