DATASHEET
3.3 VOLT COMMUNICATIONS CLOCK PLL
Description
The MK2049-44 is a dual Phase-Locked Loop (PLL) device
which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate input
jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop filter
component selection.
Buffer Mode accepts a 10 to 50MHz input and will provide a
jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK.
In this mode the MK2049-44 is ideal for filtering jitter from
high frequency clocks.
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This allows
for the generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems.
ICS can customize these devices for many other different
frequencies. Contact your ICS representative for more
details.
MK2049-44
Features
•
Packaged in 20 pin SOIC
•
3.3 V + 5% operation
•
Meets the TR62411, ETS300 011, and GR-1244
•
•
•
•
•
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, or 10 to
50 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1 / x0.5 or x1 / x2 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3, and OC3
submultiples
Block Diagram
R
SET
ISET
C
P
C
S
R
S
CAP2
C
L
CAP1 X1
C
L
Optional Crystal Load Caps
External Pullable Crystal
X2
ICLK
Reference
Divider
(used in buffer
mode only)
Phase
Detector
VCXO
Charge
Pump
Reference
Divider
VCO
Output
Divider
Divide
by 2
CLK
CLK/2
VCXO
PLL
Feedback
Divider (N)
Translator
PLL
Feedback
Divider
8k
4
FS3:0
Divider Value
Look-up Table
IDT™ / ICS™
3.3 VOLT COMMUNICATIONS CLOCK PLL
1
MK2049-44
REV A 050203
MK2049-44
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Pin Assignment
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
RES
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
20 pin 300 mil SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RES
FS0
Pin
Type
Input
Input
Input
Power
-
Power
Power
Output
Output
Output
Input
Input
Input
Power
Power
Loop
Filter
Power
Loop
-
Input
Pin Description
Frequency select 1. Determines CLK input/outputs per table on page 2.
Crystal connection. Connect to a MHz crystal as shown in table on page 2.
Crystal connection. Connect to a MHz crystal as shown in table on page 2.
Power supply. Connect to +3.3V.
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
Power supply. Connect to +3.3V.
Connect to ground
Clock output determined by status of FS3:0 per tables on page 2.
Clock output determined by status of FS3:0 per tables page 2. Always 1/2 of
CLK.
Recovered 8 kHz clock output.
Frequency select 2. Determines CLK input/outputs per table on page 2.
Frequency select 3. Determines CLK input/outputs per table on page 2.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Power Supply. Connect to +3.3V.
Connect the loop filter capacitors and resistor between this pin and CAP2.
Connect to ground.
Connect the loop filter capacitors and resistor between this pin and CAP1.
Connect a resistor to ground. See table.
Frequency select 0. Determines CLK input/outputs per table on page 2.
IDT™ / ICS™
3.3 VOLT COMMUNICATIONS CLOCK PLL
2
MK2049-44
REV A 050203
MK2049-44
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Output Decoding Table - External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
1
1
FS1
0
0
1
1
0
0
1
1
1
1
0
0
FS0
0
1
0
1
0
1
0
1
0
1
0
1
CLK/2
1.544
2.048
22.368
17.184
19.44
12.8
25.92
4.096
24.576
16.384
17.28
62.5
CLK
3.088
4.096
44.736
34.368
38.88
25.6
51.84
8.192
49.152
32.768
34.56
125
8k
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
Crystal
Used (MHz)
12.352
12.288
11.184
11.456
9.72
8.192
17.664
9.344
15.36
10.752
10.24
9.72
N
1544
1536
1398
1432
1215
1024
2208
1168
1920
1344
1280
1215
Output Decoding Table - Loop Timing Mode (MHz)
ICLK
1.544
2.048
FS3
1
1
FS2
0
0
FS1
0
0
FS0
0
1
CLK/2
1.544
2.048
CLK
3.088
4.096
8k
N/A
N/A
Crystal
12.352
12.288
N
24
18
Output Decoding Table - Buffer Mode (MHz)
ICLK
19 - 36
10 - 18
FS3
1
1
FS2
1
1
FS1
1
1
FS0
0
1
CLK/2
ICLK/2
2*ICLK
CLK
ICLK
4*ICLK
8k
N/A
N/A
Crystal
ICLK/2
ICLK
N
3
3
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Functional Description
The MK2049-44 is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2049-44 is configured
to provide a high frequency communications reference clock
output from an 8 kHz input clock or to jitter attenuate and
buffer a high frequency input clock. There are 12 selectable
output frequencies, two buffer mode selections and a loop
timing mode. Please refer to the Output Clock Selection
Table on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2049-44 is able to
generate a low jitter, low phase-noise output clock within a
low bandwidth PLL. This serves to provide input clock jitter
attenuation and enables stable operation with a low
frequency reference clock.
The VCXO circuit requires an external pullable crystal for
operation. External loop filter components enable a PLL
configuration with low loop bandwidth.
IDT™ / ICS™
3.3 VOLT COMMUNICATIONS CLOCK PLL
3
MK2049-44
REV A 050203
MK2049-44
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Application Information
Output Frequency Configuration
The MK2049-44 is configured to generate a set of output
frequencies from an 8 kHz input clock. Please refer to the
Output Clock Selection Table on Page 2. Input bits FS3:0
are set according to this table, as is the external crystal
frequency. Please refer to the Quartz Crystal section on this
page regarding external crystal requirements.
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components R
S
,
C
S
and C
P
. R
SET
establishes PLL charge pump current and
therefore influences loop filter characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK2049-44. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK2049-44 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK2049-44 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK2049-44 are designed
to have zero frequency when the total of on-chip + stray
capacitance is 14 pF. To achieve this, the layout should use
short traces between the MK2049-44 and the crystal.
A complete description of the recommended crystal
parameters in the ICS application note, MAN05.
To obtain a list of qualified crystal devices please visit our
website at:
http://www.icst.com/products/telecom/vcxocrystals.htmor
email telecom@icst.com
CAP2
C2
5.6nF
CAP1
R
Z
750 kΩ
C1 0.56µF
Figure 3. Typical Loop Filter
A “normalized” PLL loop bandwidth may be calculated as
follows:
R
S
×
I
CP
×
575
NBW
= ---------------------------------------
-
N
The “normalized” bandwidth equation above does not take
into account the effects of damping factor or the second
pole. However, it does provide a useful approximation of
filter performance.
The loop damping factor is calculated as follows:
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating
stability. The MK2049-44 uses external loop filter
components for the following reasons:
1) Larger loop filter capacitor values can be used, allowing
625
×
I
CP
×
C
S
Damping Factor = R
S
×
-----------------------------------------
-
N
Where:
R
S
= Value of resistor in loop filter (Ohms)
I
CP
= Charge pump current (amps)
IDT™ / ICS™
3.3 VOLT COMMUNICATIONS CLOCK PLL
4
MK2049-44
REV A 050203
MK2049-44
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
C
S
= Value of capacitor C
S
in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C
S
and C
P
in the loop
filter:
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2049-44 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK2049-44 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
C
P
≤
------
20
C
S
Charge Pump Current Table
R
SET
(kΩ)
13
15
16
18
20
22
24
27
36
47
56
75
100
150
200
Charge Pump Current
(I
CP
) (µA)
174
150
139
121
106
95
85
74
52
38
30
21
15
10
7
Recommended Power Supply Connection for
Optimal Device Performance
V D D P in
C onnection to 3.3V
P ow er P lane
Ferrite
Bead
V D D P in
B ulk D ecoupling C apacitor
(such as 1 F Tantalum )
V D D P in
0.01
F D ecoupling C apacitors
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground,
shown as C
L
in the External Component Schematic. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no via’s) been the crystal and device.
In most cases the load capacitors will not be required. They
should not be stuffed on the prototype evaluation board as
the indiscriminate use of these trim capacitors will typically
cause more crystal centering error than their absence. If the
need for the load capacitors is later determined, the values
will fall within the 1-4 pF range. The need for, and value of,
these trim capacitors can only be determined at prototype
Special considerations must be made in choosing loop
components C
S
and C
P
. These recommendations can be
found at
http://www.icst.com/products/telecom/loopfiltercap.htm
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω. (The
optional series termination resistor is not shown in the
External Component Schematic.)
IDT™ / ICS™
3.3 VOLT COMMUNICATIONS CLOCK PLL
5
MK2049-44
REV A 050203
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