Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES
•
Wide supply voltage range from 1.65 to 3.6 V
•
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
•
3.6 V tolerant inputs/outputs
•
CMOS LOW power consumption
•
Direct interface with TTL levels (2.7 to 3.6 V)
•
Power-down mode
•
Latch-up performance exceeds
≤250
mA
•
ESD protection:
2000 V Human Body Model (JESD22-A114-A)
200 V Machine Model (JESD22-A115-A).
DESCRIPTION
74ALVC373
The 74ALVC373 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC373 is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
internal latches.
The 74ALVC373 consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state
each time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The ‘373’ is functionally identical to the ‘573’, but the ‘573’
have a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay inputs D
n
to output Q
n
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
outputs enable
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
and the latch is in transparent mode.
35
14
pF
pF
TYP.
3.0
2.3
2.4
2.2
3.5
UNIT
ns
ns
ns
ns
pF
2002 Feb 26
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS
74ALVC373D
74ALVC373PW
FUNCTION TABLE
See note 1.
INPUT
OPERATING MODES
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
PINNING
PIN
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
SYMBOL
OE
Q
0
to Q
7
D
0
to D
7
GND
LE
V
CC
3-state latch output
data input
ground (0 V)
latch enable input (active HIGH)
supply voltage
DESCRIPTION
output enable input (active LOW)
L
L
L
L
H
H
LE
H
H
L
L
X
L
D
n
L
H
l
h
X
h
20
20
PACKAGE
SO
TSSOP
MATERIAL
plastic
plastic
74ALVC373
CODE
SOT163-1
SOT360-1
INTERNAL
LATCHES
L
H
L
H
X
H
OUTPUTS
Q
0
to Q
7
L
H
L
H
Z
Z
2002 Feb 26
3