Disabled outputs programmable as HiZ or Active Low.
•
Low current consumption:
o
< 1.2mA @ 27MHz
o
< 5µA when PDB is activated
•
Single 1.8V to 3.3V, ± 10% power supply
•
Operating temperature range from -40°C to 85°C
•
Available in 6-pin DFN, SOT23, and SC70
GREEN/RoHS compliant packages.
DESCRIPTION
The PL611s-28 consumes very low-power while
producing high performance clock outputs of up to
125MHz. Designed for low-power applications with
very stringent space requirement, PL611s-28
consumes about 1.2mA, while producing 2 distinct
outputs of 27MHz and 13.5MHz. Designed to fit in a
small SOT23, SC70, or DFN package for high
performance applications, the PL611s-28 offers the
best phase noise and jitter performance, and power
consumption of its rivals. The power down feature of
PL611s-28, when activated, allows the IC to
consume less than 5µA of power, while its
programming flexibility allows generating any output,
using a low-cost crystal or reference input. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(F
OUT
, F
REF
, F
REF
/2) output.
PACKAGE PIN CONFIGURATION
GND
PL611s-28
PL611s-28
PL611s-28
1
2
3
6
5
4
CLK0
VDD
OE, PDB,
FSEL, CLK1
GND
XIN, FIN
1
2
3
6
5
4
CLK0
VDD
XOUT
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
PL611s-28
XIN, FIN
OE, PDB, FSEL, CLK1
GND
1
2
3
6
5
4
XOUT
VDD
CLK0
OE, PDB,
FSEL, CLK1
XIN, FIN
XOUT
SOT23-
SOT23-6L
23
35mm
mm)
(3.0 x 3.0 x 1.35mm)
DFN-
DFN-6L
mm)
(2.0 x 1.3 x 0.6mm)
SC70-
SC70-6L
70
mm)
(2.3 x 2.25 x 1.0mm)
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 02/08/10 Page 1
(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK[0:1]
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths
to choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
OE - input
•
PDB - input
•
FSEL – input
•
Clock - output
•
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Pin Assignment
Name
SOT SC70 DFN
Pin # Pin# Pin#
Type
Description
This programmable I/O pin can be configured as an Output Enable
(OE) input, Power Down (PDB) input, On-the-Fly Frequency
Switching Selector (FSEL) input or CLK1 clock output. This pin has
an internal 60K pull up resistor (OE, PDB & FSEL Only).
OE, PDB,
FSEL, CLK1
1
2
2
I/O
State
0
1 (default)
GND
XIN, FIN
XOUT
VDD
CLK0
2
3
4
5
6
1
3
4
5
6
3
1
6
5
4
P
I
O
P
O
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Bank 1
Bank 2
GND connection
Crystal or Reference input pin
Crystal Output pin
Do Not Connect (DNC) when FIN is present
VDD connection
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 02/08/10 Page 2
(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
FUNCTIONAL DESCRIPTION
The PL611s-28 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-28 accepts a fundamental input crystal of 10MHz to 50MHz or
reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible
design allows the PL611s-28 to deliver any PLL generated frequency, F
REF
(Crystal or Ref Clk) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-28 are mentioned below:
PLL Programming
The PLL in the PL611s-28 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by the
following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (F
VCO
/(2*P)),
F
REF
(Crystal or Ref Clk Frequency) output, or
F
REF
/(2*P) output.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-28 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference (Crystal or Ref Clk) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
The output drive level can be programmed to Low
Drive (4mA), Standard Drive (8mA) or High Drive
(16mA) for each clock, independently.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-28 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<5µA of power. The PDB pin incorporates a 60k
pull up resistor giving a default condition of logic “1”.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-28 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull
up resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 02/08/10 Page 3
(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
T
S
10
-65
-40
150
85
SYMBOL
V
DD
V
I
V
O
MIN
-0.5
-0.5
-0.5
MAX
4.6
V
DD
+0.5
V
DD
+0.5
260
UNITS
V
V
V
°C
Year
°C
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
V
DD
=3.3V, 27MHz,
load=15pF
V
DD
=2.5V, 27MHz,
load=10pF
V
DD
=1.8V, 27MHz,
load=5pF
V
DD
=3.3V, 27MHz,
load=15pF
V
DD
=2.5V, 27MHz,
load=10pF
V
DD
=1.8V, 27MHz,
load=5pF
When PDB=0
1.62
Time for V
DD
to reach 90%
V
DD
. Power ramp must be
monotonic.
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
4
8
16
MIN
TYP
3.7
2.3
1.3
3.4
1.9
1
5
3.63
100
0.4
µA
V
ms
V
V
mA
mA
mA
mA
mA
MAX
UNITS
Supply Current, Dynamic
I
DD
PLL Off: Supply Current, Dynamic
I
DD
Supply Current, Dynamic
Operating Voltage
Power Supply Ramp
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
I
DD
V
DD
t
PU
V
OL
V
OH
I
OSD
I
OSD
I
OHD
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 02/08/10 Page 4
(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN
10
1
0.9
0.1
TYP
MAX
50
200
166
133
V
DD
V
DD
125
1
90
65
2
10
2
-2
1.2
1.2
45
50
70
2
1.7
1.7
55
Vpp
Vpp
MHz
MHz
MHz
ms
ns
ms
ppm
ns
ns
%
ps
MHz
UNITS
MHz
Crystal Input Frequency (XIN) Fundamental Crystal
@ V
DD
=3.3V
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
Output Frequency
Settling Time
Output Enable Time
VDD Sensitivity
Output Rise Time
Output Fall Time
Duty Cycle
Period Jitter,Pk-to-Pk*
(10,000 samples measured)
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load. Add one
clock period to this measurement for a usable
clock output.
PDB Function; Ta=25º C, 15pF Load
Frequency vs. V
DD
+/-10%
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
V
DD
/ 2
With capacitive decoupling between V
DD
and GND
* Note: Jitter performance depends on the programming parameters.
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range)
SYMBOL
F
XIN
C
L (xtal)
MIN
10
8
TYP
MAX
50
12
100
UNITS
MHz
pF
µW
µW
pF
pF
Maximum Sustainable Drive Level
Operating Drive Level
Metal Can Crystal
Small SMD Crystal
Shunt Capacitance
ESR Max
Shunt Capacitance
ESR Max
C0
ESR
C0
ESR
30
5.5
50
2.5
80
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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