TSPC603e with
inverted leads
PowerPC 603e™ RISC MICROPROCESSOR Family
PID6-603e Specification
DESCRIPTION
The PID6-603e implementation of PC603e (after named 603e)
is a low-power implementation of reduced instruction set com-
puter (RISC) microprocessors PowerPC™ family. The 603e
implements 32-bit effective addresses, integer data types of 8,
16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603e is a low-power 3.3-volt design and provides four soft-
ware controllable power-saving modes.
The 603e is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603e makes completion appear sequential. The 603e inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603e provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603e has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603e interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603e supports single-beat and burst data
transfers for memory accesses, and supports memory-
mapped I/O.
The 603e uses an advanced, 3.3-V CMOS process technology
and maintains full interface compatibility with TTL devices.
The 603e integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
CERQUAD 240
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
with inverted leads
MAIN FEATURES
H
2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated)
H
Superscalar (3 instructions per clock peak).
H
Dual 16KB caches.
H
Selectable bus clock.
H
32-bit compatibility PowerPC implementation.
H
On chip debug support.
H
P
D
typical = 3.2 Watts (100 MHz), full operating conditions.
H
Nap, doze and sleep modes for power savings.
H
Branch folding.
H
64-bit data bus (32-bit data bus option).
H
4-Gbyte direct addressing range.
H
Pipelined single/double precision float unit.
H
H
H
H
IEEE 754 compatible FPU.
IEEE P 1149-1 test mode (JTAG/C0P).
f
int
max = 100/120/133 MHz.
f
bus
max = 66 MHz.
Compatible CMOS input
TTL Output.
See TSPC603e ”PRODUCT SPECIFICATION” of June 1998
for functional and electrical informations.
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
H
According to TCS standards
H
MIL-STD-883 class Q (tbc)
H
Full military temperature range (T
c
= -55°C, T
c
= +125°C)
Industrial temperature range
(T
c
=
–
40°C, T
c
= +110°C)
H
V
CC
= 3.3 V
±
5 %.
H
240 pin Cerquad with inverted leads.
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December 1998
TSPC603e
2. PACKAGE MECHANICAL DATA
240 pins - CQFP
Notes :
1. Dimensioning and tolerancing per
ASME Y14.5M–1994
2. Controlling dimension : millimeter.
3. Datum plane H is located at bottom
of lead and is coincident with the lead
where the lead exits the ceramic body
at the bottom of the parting line.
4. Datum L. M and N to be determined
at datum plane H.
5. Dimension S and V to be determined
at seating plane T.
6. Dimension A and B define maximum
ceramic body dimensions including
glass protrusion and top and bottom
mismatch.
MILLIMETERS
MIN
TYP
30.86
31.00
30.86
31.00
3.67
3.95
0.185
0.220
3.10
3.50
0.175
0.200
0.50 BSC
2.025
2.100
0.130
0.147
0.45
0.50
0.25 BSC
34.41
34.58
17.20
17.30
34.41
34.58
0.25
0.50
17.20
17.30
0.122
0.127
1.80 REF
0.95 REF
1°
4°
DIM
A
B
C
D
E
F
G
HE
J
K
P
S
U
V
W
Y
Z
AA
AB
q2
MAX
31.75
31.75
4.15
0.270
3.90
0.225
2.175
0.175
0.55
34.75
17.40
34.75
0.75
17.40
0.132
7°
Figure 2 : Mechanical dimensions of the Wire-bond CQFP package
3/4
TSPC603e
3. ORDERING INFORMATION
TS (X) PC603E M A
I
B/C 3
L
(N)
TCS prefix
(1)
Prototype
Type
L
:
Revision level
Bus divider
Any bus
≤
66 MHz
Temperature range : Tc
M:
V:
–55, +125
°C
–40, +110
°C
Max internal processor speed
(2)
3
: 100 MHz
: 120 MHz
: 133 MHz
Package
A
:
CERQUAD
4
5
Screening level
(2)
Inverted leads
I
:
Inverted
__
:
Standard
MIL-STD-883, class Q (tbc)
According to MIL-STD-883 (tbc)
B/Q :
B/T :
(1) THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
(2) For availability of the different versions, contact your TCS sale office
Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of THOM-
SON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to change without notice.
This publication supersedes and replaces all information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFI-
QUES products are not authorized for use as critical components in life support devices or systems without express written approval
from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.
The PowerPC names and logo type are trademarks of International Business Machines Corporation, used under licence.
©
1998 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Printed in France - All rights reserved.
This product is manufactured and commercialized by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Avenue de Roche-
plaine PO Box 123 - 38521 SAINT-EGREVE Cedex - FRANCE.
For further information please contact :
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Départementale 128 - PO Box 46 - 91401 ORSAY Cedex -
FRANCE - Phone +33 (0)1 69 33 00 00 - Fax +33 (0)1 69 33 03 21 - Telex 616780 F TCS - Email: lafrique@tcs.thomson.fr
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