32-Bit TX System RISC
TX39 Family
TMPR3927
MIPS16, application Specific Extensions and R3000A are a trademark of MIPS
Technologies, Inc.
The information contained herein is subject to change without notice.
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Table of Contents
Table of Contents
Handling precautions
1. Outline and Features................................................................................................................................................1-1
1.1
Outline ............................................................................................................................................................1-1
1.2
Notation Used in This Manual........................................................................................................................1-2
1.2.1
Numerical Notation................................................................................................................................1-2
1.2.2
Data Notation .........................................................................................................................................1-2
1.2.3
Signal Notation ......................................................................................................................................1-2
1.2.4
Register Notation ...................................................................................................................................1-2
1.3
2.1
3.1
3.2
3.3
3.4
4.1
4.2
Features...........................................................................................................................................................1-3
Block Diagram................................................................................................................................................2-1
Pinout..............................................................................................................................................................3-1
Pin Description ...............................................................................................................................................3-3
Pin Multiplexing .............................................................................................................................................3-9
Initial Setting Signals....................................................................................................................................3-12
Memory Mapping ...........................................................................................................................................4-1
Register Mapping ...........................................................................................................................................4-3
2. Structure ..................................................................................................................................................................2-1
3. Pins..........................................................................................................................................................................3-1
4. Address Mapping ....................................................................................................................................................4-1
5. Configuration ..........................................................................................................................................................5-1
5.1
Chip Configuration Register (CCFG) 0xFFFE_E000 ....................................................................................5-1
5.1.1
Chip Revision ID Register (CRIR) 0xFFFE_E004................................................................................5-3
5.1.2
Pin Configuration Register (PCFG) 0xFFFE_E008...............................................................................5-4
5.1.3
Timeout Error Address Register (TEAR) 0xFFFE_E00C .....................................................................5-7
6. Clocks......................................................................................................................................................................6-1
6.1
6.2
Clock Generator..............................................................................................................................................6-1
System Control Clock (SYSCLK)..................................................................................................................6-1
6.3
Power-Down Mode.........................................................................................................................................6-2
6.3.1
Operation ...............................................................................................................................................6-2
6.3.2
Register ..................................................................................................................................................6-3
7. Bus Operation..........................................................................................................................................................7-1
7.1
Bus Mastership ...............................................................................................................................................7-1
7.1.1
Snoop Function ......................................................................................................................................7-1
7.1.2
Relationship Between the Endian Mode and Data Bus..........................................................................7-1
7.2
Bus Operation .................................................................................................................................................7-3
7.2.1
Bus Error................................................................................................................................................7-4
8. SDRAM Controller .................................................................................................................................................8-1
8.1
8.2
8.3
Features...........................................................................................................................................................8-1
SDRAM Block Diagram.................................................................................................................................8-3
Memory Configuration ...................................................................................................................................8-4
8.4
Registers .........................................................................................................................................................8-5
8.4.1
Register Mapping...................................................................................................................................8-5
8.4.2
SDRAM Channel Control Registers (SDCCR0-SDCCR7) ...................................................................8-6
8.4.3
SDRAM Timing Register 1 (for SDRAM/SGRAM) (SDCTR1) ..........................................................8-8
8.4.4
SDRAM Timing Register 2 (for DIMM Flash Memory ) (SDCTR2) .................................................8-10
8.4.5
SDRAM Timing Register 3 (for SMROM) (SDCTR3) .......................................................................8-11
8.4.6
SDRAM Command Register (SDCCMD) ...........................................................................................8-12
8.4.7
SGRAM Load Mask Register (SDCSMRS1) ......................................................................................8-13
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Table of Contents
8.4.8
SGRAM Load Color Register (SDCSMRS2) ......................................................................................8-13
8.5
Operation ......................................................................................................................................................8-14
8.5.1
TX3927 Signals for Different Memory Types .....................................................................................8-14
8.5.2
SDRAM Operation ..............................................................................................................................8-15
8.5.3
DIMM Flash Memory Operation .........................................................................................................8-22
8.5.4
SMROM Operation..............................................................................................................................8-25
8.5.5
SGRAM Operation ..............................................................................................................................8-27
8.5.6
Notes on Programming ........................................................................................................................8-28
8.6
Timing Diagrams ..........................................................................................................................................8-29
8.6.1
SDRAM Single Read Operation in 32-bit Bus Mode ..........................................................................8-29
8.6.2
SDRAM Single Write Operation in 32-bit Bus Mode .........................................................................8-30
8.6.3
SDRAM Burst Read Operation in 32-bit Bus Mode............................................................................8-32
8.6.4
SDRAM Burst Write Operation in 32-bit Bus Mode ...........................................................................8-33
8.6.5
SDRAM Read in 32-bit Bus Mode (Crossing Page Boundary) ...........................................................8-34
8.6.6
SDRAM Write in 32-bit Bus Mode (Crossing Page Boundary) ..........................................................8-35
8.6.7
SDRAM Slow Burst Write Operation in 32-bit Bus Mode..................................................................8-36
8.6.8
SDRAM Single Read Operation in 16-bit Bus Mode ..........................................................................8-37
8.6.9
SDRAM Single Write Operation in 16-bit Bus Mode .........................................................................8-38
8.6.10 DIMM Flash Memory Single Read Operation in 32-bit Bus Mode.....................................................8-39
8.6.11 DIMM Flash Memory Single Write Operation in 32-bit Bus Mode ....................................................8-40
8.6.12 SMROM Single Read Operation in 32-bit Bus Mode .........................................................................8-41
8.6.13 SMROM Burst Read Operation in 32-bit Bus Mode ...........................................................................8-42
8.6.14 Low Power and Power-down Mode.....................................................................................................8-43
8.6.15 SGRAM in 32-bit Bus Mode ...............................................................................................................8-46
8.6.16 External DMA Operation (Big Endian) ...............................................................................................8-49
8.6.17 External DMA Operation (Little Endian) ............................................................................................8-51
8.7
9.1
9.2
Examples of Using SDRAM ........................................................................................................................8-53
Features...........................................................................................................................................................9-1
Block Diagram................................................................................................................................................9-2
9. External Bus Controller...........................................................................................................................................9-1
9.3
Registers .........................................................................................................................................................9-3
9.3.1
Register Map..........................................................................................................................................9-3
9.3.2
ROM Channel Control Registers (RCCR0-RCCR7) .............................................................................9-4
9.4
Operation ........................................................................................................................................................9-6
9.4.1
Bootup Options ......................................................................................................................................9-6
9.4.2
Global Options .......................................................................................................................................9-7
9.4.3
ROM Channel Control Registers ...........................................................................................................9-7
9.4.4
Clock Options ........................................................................................................................................9-7
9.4.5
Base Address and Channel Size.............................................................................................................9-8
9.4.6
Operating Modes....................................................................................................................................9-8
9.4.7
16-Bit Data Bus Operation...................................................................................................................9-10
9.4.8
SHWT Option ......................................................................................................................................9-10
9.4.9
ACK*/READY Signal Timing.............................................................................................................9-11
9.4.10 READY Input Timing..........................................................................................................................9-12
9.4.11 Addressing ...........................................................................................................................................9-13
9.4.12 ACE* Operation...................................................................................................................................9-13
9.5
Timing Diagrams ..........................................................................................................................................9-14
9.5.1
ACE* Signal Operation .......................................................................................................................9-15
9.5.2
Normal Mode 32-bit Write Operation..................................................................................................9-16
9.5.3
Normal Mode 32-bit Operation............................................................................................................9-17
9.5.4
Normal Mode 16-bit Bus Operation ....................................................................................................9-20
9.5.5
Normal Mode 16-bit Burst Operation ..................................................................................................9-24
9.5.6
Page Mode 32-bit Burst Operation ......................................................................................................9-26
9.5.7
External ACK* Mode 32-bit Operation ...............................................................................................9-28
9.5.8
External ACK* Mode 16-bit Operation ...............................................................................................9-32
9.5.9
READY Mode 32-bit Operation ..........................................................................................................9-34
9.6
Examples of Using Flash ROM and SRAM .................................................................................................9-36
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10. DMA Controller ....................................................................................................................................................10-1
10.1
10.2
Features.........................................................................................................................................................10-1
Block Diagram..............................................................................................................................................10-2
10.3 Registers .......................................................................................................................................................10-3
10.3.1 Register Map........................................................................................................................................10-3
10.3.2 Master Control Register (MCR)...........................................................................................................10-4
10.3.3 Channel Control Registers (CCRn)......................................................................................................10-6
10.3.4 Channel Status Registers (CSRn).........................................................................................................10-9
10.3.5 Source Address Registers (SARn) .....................................................................................................10-11
10.3.6 Destination Address Registers (DARn) .............................................................................................10-12
10.3.7 Chained Address Registers (CHARn)................................................................................................10-13
10.3.8 Source Address Increment Registers (SAIn) .....................................................................................10-14
10.3.9 Destination Address Increment Registers (DAIn)..............................................................................10-15
10.3.10 Count Registers (CNTRn)..................................................................................................................10-16
10.4 Operation ....................................................................................................................................................10-17
10.4.1 Dual-Address Transfers......................................................................................................................10-17
10.4.2 Chaining Operations ..........................................................................................................................10-19
10.4.3 Single-Address Transfers ...................................................................................................................10-20
10.4.4 DMA Channel Termination by the External DMADONE* Input......................................................10-20
10.4.5 Restrictions on Non-standard Increment Values ................................................................................10-21
10.4.6 Restrictions on Dual-Address Burst Transfers ...................................................................................10-22
10.4.7 DMA Transfers with On-Chip I/O Peripherals ..................................................................................10-22
10.4.8 Timing for an External DMA Request (DMAREQ) ..........................................................................10-23
10.4.9 Configuration Errors ..........................................................................................................................10-23
10.4.10 Notes on Using the DMAC FIFO ......................................................................................................10-24
10.5 Timing Diagrams ........................................................................................................................................10-26
10.5.1 Single-Address Mode, 32-bit Read Operation (ROM) ......................................................................10-26
10.5.2 Single-Address Mode, 32-bit Write Operation (SRAM)....................................................................10-28
10.5.3 Single-Address Mode, 32-bit Burst-Read Operation (ROM).............................................................10-29
10.5.4 Single-Address Mode, 32-bit Burst-Write Operation (SRAM)..........................................................10-30
10.5.5 Single-Address Mode, 16-bit Read Operation (ROM) ......................................................................10-32
10.5.6 Single-Address Mode, 16-bit Write Operation (SRAM)....................................................................10-33
10.5.7 Single-Address, Half-speed Mode, 32-bit Read Operation (ROM) ...................................................10-34
10.5.8 Single-Address, Half-speed Mode, 32-bit Write Operation (SRAM) ................................................10-35
10.5.9 Single-Address Mode, 32-bit Read Operation (SDRAM) .................................................................10-36
10.5.10 Single-Address Mode, 32-bit Write Operation (SDRAM).................................................................10-37
10.5.11 Single-Address Mode, 16-bit Burst-Read Operation (SDRAM)........................................................10-38
10.5.12 Single-Address Mode, 32-bit Burst-Read Operation (SDRAM)........................................................10-39
10.5.13 Single-Address Mode, 32-bit Burst-Write Operation (SDRAM).......................................................10-40
10.5.14 Single-Address Mode, 32-bit Last Single-Read Operation (SDRAM) ..............................................10-41
10.5.15 Single-Address Mode, 16-bit Read Operation (SDRAM) .................................................................10-42
10.5.16 Single-Address Mode, 16-bit Write Operation (SDRAM).................................................................10-43
10.5.17 Single-Address Mode, 32-bit Read Operation (SDRAM) .................................................................10-44
10.5.18 Single-Address Mode, 32-bit Write Operation (SDRAM).................................................................10-45
10.5.19 Single-Address Mode, 32-bit Burst-Write Operation (SDRAM).......................................................10-46
10.5.20 Dual-Address Mode Burst Operation (SRAM to SRAM) .................................................................10-47
10.5.21 Dual-Address Mode Burst Operation (SRAM to SDRAM)...............................................................10-48
10.5.22 Dual-Address Mode Burst Operation (SDRAM to SRAM)...............................................................10-49
10.5.23 Dual-Address Mode Burst Operation (SDRAM to SDRAM)............................................................10-50
10.5.24 Dual-Address Mode Non-burst Operation (SDRAM to ROMC Device) ..........................................10-51
10.5.25 Dual-Address Mode Non-burst Operation (ROMC Device to SDRAM) ..........................................10-52
11. Interrupt Controller (IRC) .....................................................................................................................................11-1
11.1
11.2
Features.........................................................................................................................................................11-1
Block Diagram..............................................................................................................................................11-1
11.3 Registers .......................................................................................................................................................11-2
11.3.1 Register Map........................................................................................................................................11-2
11.3.2 Interrupt Control Enable Register (IRCER) 0xFFFE_C000 ................................................................11-3
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