Supertex inc.
High Speed, Integrated Ultrasound Driver IC
Features
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Drives two ultrasound transducer channels
Generates 5-level waveform
Drives 12 high voltage MOSFETs
±2.0A source and sink peak current
Up to 20MHz output frequency
12V/ns slew rate
±3ns matched delay times
Second harmonic is less than -40dB
Two separate gate drive voltages
1.8 to 3.3V CMOS logic interface
MD1711
General Description
The Supertex MD1711 is an IC for a two-channel, 5-level,
high voltage and high speed transmitter driver. It is designed
for medical ultrasound imaging applications, but can also be
used for metal flaw detection, Non-Destructive Testing (NDT),
and for driving piezoelectric transducers.
The MD1711 is a two-channel logic controller circuit with
low impedance MOSFET gate drivers. There are two sets of
control logic inputs, one for channel A and one for channel B.
Each channel consists of three pairs of MOSFET gate drivers.
These drivers are designed to match the drive requirements of
the Supertex TC6320. The MD1711 drives six TC6320s. Each
pair consists of an N-channel and a P-channel MOSFET. They
are designed to have the same impedance and can provide
peak currents of over 2.0amps.
Applications
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Medical ultrasound imaging
Piezoelectric transducer drivers
Non-Destructive Testing (NDT)
Metal flaw detection
Sonar transmitter
Typical Application Circuit
+5.0V
+10V
0.22µF
+10V
0.22µF
-10V
0.22µF
0.22µF
+10V
0.22µF
FB
6
0.1µF
40
36
35
33
45
43
DGND
42
DV
DD
2
31
AVDD1
DVDD2 DVDD2 DGND DVDD1 DVSS
DVDD1 DVDD1
30
DGND
OUTPA1
39
DV
DD
2
+100V
V
PP
1
1µF
EN
SEL
POSA / POS1A
NEGA / NEG1A
HVEN1A / POS2A
HVEN2A / NEG2A
ClampA
+3.3V
0.1µF
47
13
1
2
3
4
Control Logic
& Level
Translator
10nF
OUTNA1
37
10nF
V
NN
1
-100V
+50V
DV
DD
1
1µF
V
PP
2
1µF
5
46
VLL
MD1711
(1/2 of I/O)
OUTPA2
41
DV
DD
1
10nF
OUTNA2
34
10nF
V
NN
2
48
0.1µF
AVSS
-50V
1µF
Transducer
0V
14
15
AVSS
SUB
AVSS
DV
DD
1
0.1µF
OUTPA3
V
SS
44
OUTNA3
32
-10V
AGND
7
DGND
DVDD1 DVSS DVDD2 DVDD1 DGND DVDD2
19
0.22µF
0
18
16
21
28
26
25
TC6320
0
0V
+10V
Doc.# DSFP-MD1711
E031714
-10V
+10V
+5.0V
Supertex inc.
www.supertex.com
MD1711
Ordering Information
Part Number
MD1711FG-G
MD1711K6-G
MD1711K6-G M933
Package Options
48-Lead LQFP
Packing
250/Tray
3000/Reel
Pin Configuration
1
48
1
48
MD1711FG-G M931 48-Lead LQFP
48-Lead (7x7mm) QFN 250/Tray
48-Lead (7x7mm) QFN 2000/Reel
48-Lead LQFP
(top view)
Value
-0.5V to +5.5V
-0.5V to +15V
-0.5V to +15V
-15V to +0.5V
0°C to +125°C
-65°C to +150°C
1.2W
48-Lead QFN
(top view)
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
V
LL
logic supply voltage
AV
DD
1, DV
DD
1, positive gate drive supply
DV
DD
2, positive gate drive supply
AV
SS
, DV
SS
, negative gate drive supply
Operating temperature range
Storage temperature range
Power dissipation
Package Marking
Top Marking
YYWW
MD1711FG
LLLLLLLLL
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level may
affect device reliability. All voltages are referenced to device ground.
Package may or may not include the following marks: Si or
48-Lead LQFP
MD1711K6
LLLLLLLLL
YYWW
AAA CCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Typical Thermal Resistance
Package
48-Lead LQFP
48-Lead QFN
θ
ja
52°C/W
18°C/W
Package may or may not include the following marks: Si or
48-Lead QFN
Operating Supply Voltages and Currents
Sym
V
LL
AV
DD1
DV
DD1
DV
DD2
I
VLL
I
AVDD1
I
AVSS &
I
DVSS
I
DVDD1
I
DVDD2
Parameter
Logic supply
Positive drive bias supply
Positive gate drive supply
Positive gate drive supply
Logic supply current
Positive bias current
Negative drive and bias supply current
Positive drive current 1
Positive drive current 2
Min
+1.8
+8.0
+4.75
+4.75
-12.0
-
-
-
-
-
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 25°C)
Typ
+3.3
+10.0
-
-
-10.0
2.0
5.0
20
55
13
Max
+5.0
+12.6
+12.60
+12.60
-8.0
-
-
-
-
-
Units Conditions
V
V
V
V
V
---
---
---
---
---
AV
SS,
DV
SS
Negative gate drive and bias supply
mA
All channels on at 5.0Mhz,
no load
All channels on at 5.0Mhz,
D
VDD
2 = 5.0, no load
mA
Doc.# DSFP-MD1711
E031714
2
Supertex inc.
www.supertex.com
MD1711
Operating Supply Voltages and Currents
(cont.)
Sym
I
AVDD1Q
I
AVSSQ
I
DVDD1Q
I
DVDD2Q
I
VLLQ
Parameter
V
AVDD
1 quiescent current
V
AVSS
quiescent current
V
DVDD
1 quiescent current
V
DVDD
2 quiescent current
Logic supply current
Min
-
-
-
-
-
2.0
0.75
-
-
1.0
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 25°C)
Typ
Max
-
-
10
10
-
Units
mA
mA
µA
µA
mA
EN = low, All inputs low or
high.
DC Electrical Characteristics
P-Channel Gate Driver Outputs
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 0 to 70°C)
-
-
-
-
-
-
2.0
2.0
6.0
6.0
-
Ω
Ω
A
A
I
SINK
= 100mA
I
SOURCE
= 100mA
---
---
-
N-Channel Gate Driver Outputs
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
-
-
-
-
-
-
1.5
1.5
10
10
-
-
Ω
Ω
A
A
I
SINK
= 100mA
I
SOURCE
= 100mA
---
---
Logic Inputs
V
IH
V
IL
I
IH
I
IL
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
0.8V
LL
0
-
-1.0
-
-
-
-
V
LL
0.2V
LL
1.0
-
V
V
µA
µA
---
---
---
---
AC Electrical Characteristics
f
OUT
t
PH
t
PL
t
r
t
f
Δt
DM
Δt
DLAY
Output frequency range
Propagation delay when
output is from low to high
Propagation delay when
output is from high to low
Output rise time
Output fall time
Delay time matching
Output jitter
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 0 to 70°C)
-
-
-
-
-
-
-
-
19
19
8.0
8.0
-
30
20
-
-
-
-
±3.0
-
MHz
ns
ns
ns
ns
ns
ps
---
No load, See timing diagram
No load, See timing diagram
1000pF load, see timing
diagram
1000pF load, see timing
diagram
No load, from device to device
Standard deviation of t
D
samples (1k)
Doc.# DSFP-MD1711
E031714
3
Supertex inc.
www.supertex.com
MD1711
AC Electrical Characteristics
(cont.)
Sym
SR
HD2
Parameter
Output slew rate
2
nd
harmonic distortion
(Over operating conditions unless otherwise specified, AV
DD
1 = DV
DD
1 = DV
DD
2 = 10V, AV
SS
= DV
SS
= -10V, V
LL
= 3.3V, T
A
= 0 to 70°C)
Min
-
-
Typ
12
-40
Max
-
-
Min
V/ns
dB
Comments
Measured at TC6320 output
with 100Ω load
Power-Up Sequence
Step
1
2
Connection
AV
SS
, DV
SS
V
LL
, AV
DD
1, DV
DD
1 & DV
DD
2
Description
Negative gate drive supply and substrate bias
Logic supply, positive gate drive supply and bias
Test Circuit for Channel A
1/2 of MD1711
DV
DD
2
3x TC6320
OUT-PA1
+100V
VPP1
10nF
+10V AV
DD
1
+10V DV
DD
1
+10VDV
DD
2
+3.3V VLL
DV
DD
2
GPA1
HVOUTPA1
HVOUTA
OUT-NA1
10nF
GNA1
HVOUTNA1
VNN1
R
LOAD
100
-100V
EN
POSA/POS1A
NEGA/NEG1A
HVEN1A/POS2A
HVEN2A/NEG2A
CLAMPA
SEL
AGND
DGND
AVSS
DVSS
-10V
DV
SS
DV
DD
1
+50V
Channel A
Control
Logic and
Level
Translation
DV
DD
1
OUT-PA2
10nF
VPP2
GPA2
HVOUTPA2
DV
DD
1
OUT-NA2
10nF
GNA2
HVOUTNA2
VNN2
-50V
VPP3
OUT-PA3
GPA3
HVOUTPA3
OUT-NA3
GNA3
HVOUTNA3
VNN3
Doc.# DSFP-MD1711
E031714
4
Supertex inc.
www.supertex.com
MD1711
Truth Table for Channels A and B (For SEL = L)
Logic Control Inputs
SEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
HVEN1/
POS2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
HVEN2/
NEG2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
Clamp
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
POS/
POS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
NEG/
NEG1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
V
PP
1 to V
NN
1 Output V
PP
2 to V
NN
2 Output V
PP
3 to V
NN
3 Output
HV
OUT
P1
HV
OUT
N1
HV
OUT
P2
HV
OUT
N2
HV
OUT
P3
ON
ON
ON
OFF
HV
OUT
N3
ON
ON
ON
OFF
Doc.# DSFP-MD1711
E031714
5
Supertex inc.
www.supertex.com
stm32/stm8
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