HD66351 (TFT Driver)
256-level Grayscale Driver for the TFT
Liquid Crystal Display for XGA/SXGA Systems
ADE-207-341
Rev.1.0
June 2001
Description
The HD66351 is a TFT driver LSI suitable for XGA and SXGA systems (eight HD66351s used). It
receives 8-bit-per-pixel digital display data, and generates and outputs voltages for 256 grayscales. The
output circuit includes an operational amplifier and is capable of alternating outputs of positive-polarity and
negative-polarity voltages on individual output pins. This results in a high-quality display with minimal
crosstalk.
Features
•
High-speed operation
Operating clock: 45 MHz
•
Operational power-supply voltage range
V
CC
= 2.5 to 3.6 V
V
LCD
= 14.5 to 15.5 V
•
LCD drive voltage
Low-voltage side: GND + 0.2 to V
LCD
/2 (V)
High-voltage side: V
LCD
/2 to V
LCD
– 0.2 (V)
•
LCD drive outputs
Eight 384-output LSIs for XGA and
Ten 384-output LSIs for SXGA
•
Output voltage deviation of
±4
mV (typ)
•
Reference power-supply pins for gamma compensation
The HD66351 has 18 reference power-supply pins, enabling gamma compensation according to the
characteristics of the liquid crystal.
HD66351
•
Multicolor display
The HD66351 receives 8-bit-per-pixel digital display data, and selects and outputs a display voltage
from 256 grayscale voltages, enabling a maximum of 16,770,000 display colors when using R/G/B
color filters.
•
48 data bits (8 grayscale code bits
×
RGB
×
2 ports)
•
Dot inversion drive
The voltage can be alternated between positive polarity and negative polarity on individual output
pins, allowing a dot-by-dot inversion drive even with a single-sided layout configuration. This
provides a high-quality display with minimal crosstalk. Also, since both positive-polarity and
negative-polarity voltages are generated by an externally provided reference power supply, gamma
compensation is enabled according to the characteristics of the liquid crystal.
•
N-raster-row inversion drive
The polarity can be inverted by each N-raster-rows. The charge or discharge current under the TFT
load can be lowered and flicker on the specific display can be reduced.
•
Operational amplifier
The output circuit includes an operational amplifier, which enables the external reference power
supply circuit to be configured using only resistance ladders. In addition, use of the chopper-type
amplifier eliminates output voltage deviations between frames and ensures high-quality displays.
•
Bidirectional shift
•
Start-pulse signal generation circuit
•
Package
TCP (customized package dimensions)
•
Supported systems
XGA (1,024
×
768 dot) and SXGA (1,280
×
1,024 dot), and other OA equipment such as notebook
PCs or monitors
2
HD66351
Pin Arrangement
Y384
Y383
Y382
Y381
Y380
Y379
Y378
Y377
Y376
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Top View
The TCP package dimensions
are not standardized.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EIO2
D57
D56
D55
D54
D53
D52
D51
D50
D47
D46
D45
D44
D43
D42
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D41
D40
D37
D36
D35
D34
D33
D32
D31
D30
FRM
LC
VCC
SHL
V17
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
V16
V15
V14
V13
V12
V11
V10
V9
VLCD
GND2
V8
V7
V6
V5
V4
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
V3
V2
V1
V0
GND1
CL2
CL1
M
POL2
POL1
D27
D26
D25
D24
D23
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
D22
D21
D20
D17
D16
D15
D14
D13
D12
D11
D10
D07
D06
D05
D04
76
77
78
79
80
D03
D02
D01
D00
EIO1
Figure 1 Pin Arrangement
3
HD66351
Internal Block Diagram
CL2
EIO1
Clock control
EIO2
M
SHL
CL1
D57 to D50, D47 to D40,
Data
D37 to D30, D27 to D20,
inversion
D17 to D10, D07 to D00
circuit
POL1
POL2
V
LCD
V
CC
GND1, 2
Grayscale voltage
generation
256 positive-polarity
grayscales
Latch address selector
8 planes
384 latch circuits (1)
8 planes
384 latch circuits (2)
V0 to V8
384 decoders
256 negative-polarity
grayscales
V9 to V17
FRM
LC
384 output amplifier circuits
Y1Y2Y3Y4
Y384
Figure 2 Block Diagram
1. Clock control unit
Generates the start-pulse signals (EIO1, EIO2) and controls internal timing signals.
2. Data inversion circuit
Uses the POL1 and POL2 signals to perform polarity inversion (at high levels) or non-inversion (at low
levels) processing of input display data.
3. Latch address selector
Generates latch signals for sequentially latching the input display data.
4. Latch circuits (1)
384
×
8-bit latch circuits that sequentially latch 6-output
×
8-bit input display data.
5. Latch circuits (2)
Performs latching, in synchronization with CL1, of the 384
×
8-bit data latched by latch circuits (1).
4
HD66351
6. Decoders
Decodes the 8-bit data and selects the liquid-crystal application voltages.
7. Grayscale voltage generation unit
Performs resistance-division of the external input voltage, and generates 256 positive-polarity
grayscales and 256 negative-polarity grayscales.
8. Output amplifier circuits
Outputs the grayscale voltage that has been selected for each output and buffered in the operational
amplifier.
5
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