Low Cost Gigabit Rate
Transmit/Receive Chip Set
Technical Data
HDMP-1012 Transmitter
HDMP-1014 Receiver
Features
•
Transparent, Extended
•
•
•
•
•
Ribbon Cable Replacement
Implemented in a Low Cost
Aluminum M-Quad 80
Package
High-Speed Serial Rate
150-
1500 MBaud
Standard 100K ECL
Interface
16, 17, 20, or 21 Bits Wide
Reliable Monolithic Silicon
Bipolar Implementation
On-chip Phase-Locked Loops
- Transmit Clock Generation
- Receive Clock Extraction
Description
The HDMP-1012 transmitter and
the HDMP-1014 receiver are used
to build a high speed data link for
point to point communication.
The monolithic silicon bipolar
transmitter chip and receiver chip
are each provided in a standard
aluminum M-Quad 80 package.
From the user’s viewpoint, these
products can be thought of as
providing a “virtual ribbon cable”
interface for the transmission of
data. Parallel data loaded into the
Tx (transmitter) chip is delivered
to the Rx (receiver) chip over a
serial channel, which can be
either a coaxial copper cable or
optical link.
The chip set hides from the user
all the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding.
Unlike other links, the phase-
locked-loop clock extraction
circuit also transparently provides
for frame synchronization - the
user is not troubled with the
periodic insertion of frame
synchronization words. In
addition, the dc balance of the
line code is automatically
maintained by the chip set. Thus,
the user can transmit arbitrary
data without restriction. The Rx
chip also includes a state-machine
controller (SMC) that provides a
startup handshake protocol for
the duplex link configuration.
The serial data rate of the T/R link
is selectable in four ranges (see
tables on page 5), and extends
from 120 Mbits/s up to 1.25
Gbits/s. The parallel data interface
is 16 or 20 bit single-ended ECL,
pin selectable. A flag bit is
available and can be used as an
extra 17th or 21st bit under the
user’s control. The flag bit can
also be used as an even or odd
frame indicator for dual-frame
transmission. If not used, the link
performs expanded error
detection.
The serial link is synchronous,
and both frame synchronization
Applications
•
Backplane/Bus Extender
•
Video, Image Acquisition
•
Point to Point Data Links
•
Implement SCI-FI Standard
•
Implement Serial HIPPI
Specification
5962-0049E (6/94)
573
and bit synchronization are
maintained. When data is not
available to send, the link
maintains synchronization by
transmitting fill frames. Two
(training) fill frames are reserved
for handshaking during link
startup.
User control space is also sup-
ported. If Control Available is
asserted at the Tx chip, the least
significant 14 or 18 bits of the
data are sent and the Rx Control
Available line will indicate the
data as a Control Word.
It is the intention of this data
sheet to provide the design
engineer all of the information
regarding the HDMP-1012/1014
chipset necessary to design this
product into their application. To
assist you in using this data sheet,
the following Table of Contents is
provided.
Table of Contents
Topic
Page
Typical Applications ....................................................................... 575
Setting the Operating Rate ..............................................................576
Transmitter Block Diagram .............................................................578
Receiver Block Diagram ................................................................. 580
Transmitter Timing Characteristics ................................................ 582
Receiver Timing Characteristics ..................................................... 583
DC Electrical Specifications ........................................................... 584
AC Electrical Specifications ............................................................ 584
Typical Lock-Up Times ................................................................... 584
Absolute Maximum Ratings ............................................................ 585
Thermal Characteristics ................................................................. 585
I/O Type Definitions ....................................................................... 585
Pin-Out Diagrams .......................................................................... 586
Transmitter Pin Definitions ............................................................ 587
Receiver Pin Definitions ................................................................. 591
Mechanical Dimensions and
Surface Mount Assembly Instructions ......................................... 595
Appendix I: Additional Internal
Architecture Information
........................................................596
Line Code Description .................................................................... 596
Data Frame Codes ......................................................................... 596
Control Frame Codes ..................................................................... 597
Fill Frame Codes ............................................................................ 598
Tx Operation Principles ................................................................. 599
Tx Encoding .................................................................................. 599
Tx Phase Locked Loop ....................................................................600
Rx Operation Principles ................................................................. 601
Rx Encoding ................................................................................... 601
HDMP-1014 (Rx) Phase Locked Loop ............................................ 601
HDMP-1014 (Rx) Decoding ............................................................602
HDMP-1014 (Rx) Link Control State
Machine Operation Principle ....................................................... 603
The State Machine Handshake Protocol ..........................................603
Appendix II: Link Configuration Examples
............................. 605
Duplex/Simplex Configurations ...................................................... 605
Full Duplex .....................................................................................605
Simplex Method I: Simplex with Low Speed Return Path ............... 606
Simplex Method II: Simplex with Periodic Sync Pulse ....................607
Simplex Method III: Simplex with
External Reference Oscillator ......................................................607
Data Interface for Single/Double Frame Mode ................................ 608
Single Frame Mode (MDFSEL=0) .................................................. 608
Double Frame Mode (MDFSEL=1) ................................................ 609
Supply Bypassing and Integrator Capacitor .................................... 610
Integrating Capacitor ......................................................................610
Power Supply Bypassing and Grounding ........................................ 610
Electrical Connections .................................................................... 611
I-ECL and O-ECL ............................................................................ 611
High Speed Interface: I-H50 & O-BLL ............................................612
TTL and Positive 5 V Operation ...................................................... 613
Mode Options ................................................................................. 614
574
Typical Applications
The HDMP-1012/1014 chipset
was designed for ease of use and
flexibility. This allows the
customer to tailor the use of this
product, through the configura-
tion of the link, based on their
specific system requirements and
application needs. Typical
applications range from
backplane and bus extension to
digital video transmission.
Low latency bus extension of a 16
or 20 bit wide data bus may be
achieved using the standard
duplex configuration (see Figure
1d). In full duplex, the HDMP-
1012/1014 chipset handles all of
the issues of link startup, main-
tenance, and simple error
detection.
If the bus width is 32 or 40 bits
wide, the HDMP-1012/1014
chipset is capable of sending the
large data frame as two separate
frame segments, as shown in
Figure 1b. In this mode, called
Double Frame Mode, the FLAG
bit is used by the transmitter and
receiver to indicate the first or
second frame segment. The
HDMP-1012/1014 chipset in
Double Frame Mode may also be
configured in full duplex to
achieve a 32/40 bit wide bus
extension.
For digital video transmission,
simplex links are more common.
The HDMP-1012/1014 chipset
can transmit 16 to 21 bits of
parallel data in standard or
broadcast simplex mode.
Additionally, 32 to 40 bit wide
data can be transmitted over a
single line (in Double Frame
Mode) or two parallel lines, as in
Figure 1c.
Tx
CLK
A) 16/20 BIT SIMPLEX TRANSMISSION
Rx
CLK
MUX
CLK
Tx
Rx
CLK
DEMUX
B) 32/40 BIT SIMPLEX TRANSMISSION
Tx
CLK
Rx
CLK
Tx
CLK
Rx
CLK
C) 32/40 BIT SIMPLEX TRANSMISSION
WITH HIGH CLOCK RATES
Tx
CLK
Rx
CLK
Rx
CLK
Tx
CLK
D) 16/20 BIT DUPLEX TRANSMISSION
Tx
CLK
Rx
CLK
Rx
CLK
.
.
.
.
.
.
.
.
Rx
CLK
E) SIMPLEX BROADCAST TRANSMISSION
Figure 1. Various Configurations Using the HDMP-1012/1014.
575
For timing diagrams for the
standard configurations, see the
Appendix section entitled
Link
Configuration Examples.
The HDMP-1012/1014 chipset
can support serial transmission
rates from 150 MBd to 1.5 GBd
for each of these configurations.
The chipset requires the user to
input the link data rate by
asserting DIV1 and DIV0
accordingly. To determine the
DIV1/DIV0 setting necessary for
each application, refer to the
section:
Setting the Operating
Data Rate Range
on the next
page.
It is desired to transmit a 20 bit
parallel word operating at 55 MHz
(55 MWord/sec). Both the Tx and
Rx must be set to a range that this
word rate falls in-between.
According to table entitled
“Typical Operating Rates for 20
Bit Mode” on the next page, a
setting of DIV1/DIV0 = logic ‘0/0’
allows a parallel input word rate
of 32.9 to 62.5 MHz . This setting
easily accommodates the required
55 MHz word rate. The user serial
data rate can be calculated as:
Serial
Data Rate
20 bit
55 Mw
= (––––––) (––––––)
word
sec
= 1100 MBits/sec
Setting the Operating
Data Rate Range
The HDMP-1012/1014 chipset
can operate from 150 MBaud to
1500 MBaud. It is divided into
four operating data ranges with
each range selected by setting
DIV1 and DIV0 as shown in the
tables below.
The purpose of following example
is to help in understanding and
using these tables. This specific
example uses the table in figure 3
entitled “Typical 20-bit Mode Data
Rates”.
The baud rate includes an
additional 4 bits that G-LINK
transmits for link control and
error detection. The serial baud
rate is calculated as:
Serial
24 bits
55 Mw
Baud Rate = (––––––) (––––––)
word
sec
= 1320 MBaud
The 55 MHz example is one in
which the parallel word rate
provides only one possible DIV1/
DIV0 setting.
Some applications may have a
parallel word rate that seems to fit
two ranges. As an example, a 35
MHz (35 MWord/s) parallel data
rate fall within two ranges (DIV0/
DIV1 = 0/0 and DIV0/DIV1 = 0/
1) in 20 Bit Mode. Per the table, a
setting of DIV1/DIV0 = 0/1 gives
an upper rate of 53.3 MHz , while
a setting of DIV1/DIV0 = 0/0
gives a lower rate of 32.9 MHz.
These transition data rates are
stated in the tables as typical
values and may vary between
individual parts. Each transmitter/
receiver has continuous band
cover across its entire 150 to
1500 MBaud range and has
overlap between ranges. Each
transmitter/receiver will permit a
35 MHz parallel data rate, but it is
suggested that DIV0 be a jumper
that can be set either to logic ‘1’
(ground) or logic ‘0’ (open). This
allows the design to accommodate
both ranges for maximum
flexibility. This technique is
recommended whenever
operating near the maximum and
minimum of two word rate
ranges. The above information
also applies to the HDMP-1012/
1014 chipset when operating in
16 bit mode.
576
HDMP-1012 (Tx), HDMP-1014 (Rx)
Typical Operating Rates For 16 Bit Mode
[1]
Tc = 0°C to +85°C, V
EE
= -4.5 V to -5.5 V
Parallel Word Rate
(Mword/sec)
Range
42
75.0 (max)
21
51
11
25
7.5 (min)
13
Serial Data Rate
(Mbit/sec)
Range
672
1200.0 (max)
336
808
168
404
120.0 (min)
202
Serial Baud Rate
(MBaud)
Range
840
1500.0 (max)
420
1010
210
505
150.0 (min)
253
DIV1
0
0
1
1
DIV0
0
1
0
1
Notes:
1. Extended operating rates to 1800 MBaud/sec (typ) are possible for Tc = 0°C to +60°C.
2. All values are typical over temperature and process, unless otherwise noted by (min) or (max).
3. Typical Serial Baud Rates for DIV1/DIV0 = 0/0 are up to 1800 MBd.
4. All values in this table are expected for a BER less than 10
-14
. This estimation is based on the maximum data rate characterization,
which was performed at a serial data rate of 2000 Mbits/s for a BER less than 10
-11
. Production units are 100% screened for less than
BER = 10
-7
.
Figure 2: Typical 16-bit Mode Data Rates.
HDMP-1012 (Tx), HDMP-1014 (Rx)
Typical Operating Rates For 20 Bit Mode
[1]
Tc = 0°C to +85°C, V
EE
= -4.5 V to -5.5 V
Parallel Word Rate
(Mword/sec)
Range
35
62.5 (max)
18
42
9
21
6.3 (min)
10.5
,,,,
,,,,
,,
,,
FRAME RATE (Mwords/sec)
50
5
25
75
0/0
0/1
1/0
1/1
840
DIV 1 / DIV 0
420
1010
210
505
110
253
100
500
1000
1500
SERIAL DATA RATE (Mbaud)
100
125
1800
BAUD RATE = 20 x FRAME RATE
2000
2500
DIV1
0
0
1
1
DIV0
0
1
0
1
Serial Data Rate
(Mbit/sec)
Range
700
1250.0 (max)
350
842
175
421
125.0 (min)
211
Serial Baud Rate
(MBaud/Sec)
Range
840
1500 (max)
420
1010
210
505
150 (min)
253
Notes:
1. Extended operating rates to 1800 MBaud/sec are possible for Tc = 0°C to +60°C.
2. All values are typical over temperature and process, unless otherwise noted by (min) or (max).
3. Typical Serial Baud Rates for DIV1/DIV0 = 0/0 are up to 1800 MBd.
4. All values in this table are expected for a BER less than 10
-14
. This estimation is based on the maximum data rate characterization,
which was performed at a serial data rate of 2000 Mbits/s for a BER less than 10
-11
. Production units are 100% screened for less than
BER = 10
-7
.
Figure 3. Typical 20-Bit Mode Data Rates.
,,,,,
,,
,,,,
,,
FRAME RATE (Mwords/sec)
50
4
25
75
0/0
0/1
1/0
1/1
840
DIV 1 / DIV 0
100
1800
420
1010
210
505
BAUD RATE = 24 x FRAME RATE
110
253
100
500
1000
1500
2000
2500
SERIAL DATA RATE (Mbaud)
577
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