DATASHEET
ISL8016
6A Low Quiescent Current High Efficiency Synchronous Buck Regulator
The ISL8016 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 6A
continuous output current from a 2.7V to 5.5V input supply.
The output voltage is adjustable from 0.6V to V
IN
. With an
adjustable current limit, reverse current protection, pre-bias
start and over temperature protection the ISL8016 offers a
highly robust power solution. It uses current control
architecture to deliver fast transient response and excellent
loop stability.
The ISL8016 integrates a pair of low ON-resistance P-Channel
and N-Channel internal MOSFETs to maximize efficiency and
minimize external component count. 100% duty-cycle
operation allows less than 200mV dropout at 6A output
current. Adjustable frequency and synchronization allow the
ISL8016 to be used in applications requiring low noise.
Paralleling capability with phase interleaving allows the IC to
support >6A output current while offering reduced input and
output noise.
The ISL8016 can be configured for discontinuous or forced
continuous operation at light load. Forced continuous operation
reduces noise and RF interference while discontinuous mode
provides high efficiency by reducing switching losses at light
loads.
The ISL8016 is offered in a space saving 20 Ld 3x4 QFN lead
free package with exposed pad lead frames for excellent
thermal performance. The complete converter occupies less
than 0.15in
2
area.
Various fixed output voltages are available upon request. See
Ordering Information on page 2 for more detail.
FN7616
Rev 1.00
May 5, 2011
Features
• High Efficiency Synchronous Buck Regulator with up to 97%
Efficiency
• 1% Reference Accuracy Over-Temperature/Load/Line
• Fixed Output Voltage Option
• ±10% Output Voltage Margining
• Adjustable Current Limit
• Current Sharing Capable
• Start-up with Pre-Biased Output
• Internal Soft-Start - 1ms or Adjustable, Internal/External
Compensation
• Soft-Stop Output Discharge During Disabled
• Adjustable Frequency from 500kHz to 4MHz - Default at
1MHz
• External Synchronization up to 4MHz - Master to Slave Phase
Shifting Capability
• Peak current limiting, Hiccup Mode Short Circuit Protection
and Over-Temperature Protection‘
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Portable Instruments
• Test and Measurement Systems
• Li-ion Battery Powered Devices
100
95
EFFICIENCY (%)
90
3.3V
OUT
PFM
85
3.3V
OUT
PWM
80
75
70
0.0
1.0
2.0
3.0
I
OUT
(A)
4.0
5.0
6.0
FIGURE 1. EFFICIENCY T = +25°C V
IN
= 5V
FN7616 Rev 1.00
May 5, 2011
Page 1 of 22
ISL8016
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL8016IRAJZ
ISL8016IR12Z
ISL8016IR15Z
ISL8016IR18Z
ISL8016IR25Z
ISL8016IR33Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL8016.
For more information on MSL please see techbrief
TB363.
PART MARKING
016A
016W
016B
016C
016F
016N
OUTPUT VOLTAGE (V)
Adjustable
1.2V
1.5V
1.8V
2.5V
3.3V
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-Free)
20 Ld 3x4 QFN
20 Ld 3x4 QFN
20 Ld 3x4 QFN
20 Ld 3x4 QFN
20 Ld 3x4 QFN
20 Ld 3x4 QFN
PKG.
DWG. #
L20.3x4
L20.3x4
L20.3x4
L20.3x4
L20.3x4
L20.3x4
Pin Configuration
ISL8016
(20 LD QFN)
TOP VIEW
PGND
PGND
SGND
VFB
17
16
15
14
PAD
PHASE
VIN
VIN
4
5
6
7
VIN
8
PG
9
SYNCOUT
10
SYNCIN
13
12
11
VSET
FS
EN
COMP
SS
ISET
20
PGND
PHASE
PHASE
1
2
3
19
18
FN7616 Rev 1.00
May 5, 2011
Page 2 of 22
ISL8016
Pin Descriptions
PIN
1, 19, 20
2, 3, 4
5, 6, 7
8
9
SYMBOL
PGND
PHASE
VIN
PG
SYNCOUT
Power ground.
Switching node connection. Connect to one terminal of the inductor.
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
Power-good is an open-drain output. Use 10k to 100k pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 1V, a reset circuit will activate and discharge SYNCOUT to 0V.
SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1M pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low. There is an internal 1M pull-down resistor to prevent an
undefined logic state in case of EN pin float.
This pin sets the oscillator switching frequency, using a resistor, R
FS
, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining, and connect to VIN for +10%.
ISET is the peak output current limit and SKIP current limit setting of the regulators. Connect to SGND
for 2A, to VIN for 4A, and keep it floating for 6A.
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
Short VFB to OUTPUT when using one of the available fixed VOUT options.
Signal ground.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.
DESCRIPTION
10
SYNCIN
11
EN
12
FS
13
14
15
16, 17
VSET
ISET
SS
COMP, VFB
18
SGND
EPAD
FN7616 Rev 1.00
May 5, 2011
Page 3 of 22
ISL8016
Typical Application Diagrams
INPUT
2.7V TO 5.5V
VIN
EN
C1
2x22µF
R1
100k
PG
SYNCIN
SYNCOUT
VIN
FS
ISET
VSET
SGND
VFB
COMP
SS
* C3 is optional. Recommend
putting a placeholder for it. Check
loop analysis first before use.
R3
100k
PHASE
L
1.0µH
C2
2x47µF
PGND
R2
200k
C3*
10pF
OUTPUT
1.8V/6A
ISL8016
FIGURE 2. TYPICAL APPLICATION DIAGRAM - SINGLE CHIP 6A
TABLE 1. COMPONENT VALUE SELECTION
V
OUT
C1
C2 (or C8)
C3 (or C5)
L1 (or L2)
R2 (or R5)
R3 (or R6)
0.8V
44µF
2x47µF
10pF
0.47~1µH
33k
100k
1.2V
44µF
2x47µF
10pF
0.47~1µH
100k
100k
1.5V
44µF
2x47µF
10pF
0.47~1µH
150k
100k
1.8V
44µF
2x47µF
10pF
0.68~1.5µH
200k
100k
2.5V
44µF
2x47µF
10pF
0.68~1.5µH
316k
100k
3.3V
44µF
2x47µF
10pF
1~2.2µH
450k
100k
3.6V
44µF
2x47µF
10pF
1~2.2µH
500k
100k
FN7616 Rev 1.00
May 5, 2011
Page 4 of 22
ISL8016
L1
1.0µH
C2
2 x 47µF
OUTPUT
1.8V/12A
INPUT
2.7V TO 5.5V
VIN
EN
PHASE
C1
47µF
R1
100k
PG
VIN
ISL8016
(MASTER)
PGND
R3
100k
R2
200k
C3*
10pF
SYNCIN
SYNCOUT
FS
SGND
VFB
R4
196k
ISET
VSET
SS
COMP
C4
470pF
R3
150k
C5
10pF
C6
22nF
INPUT 2.7V TO 5.5V
VIN
EN
PG
PHASE
L2
1.0µH
C8
2 x 47µF
C7
47µF
ISL8016
(SLAVE)
PGND
SYNCOUT
SYNCIN
FS
C13
100pF
R5
249k
ISET
VSET
SS
SGND
VFB
COMP
* C3 is optional. Recommend
putting a placeholder for it. Check
loop analysis first before use.
FIGURE 3. TYPICAL APPLICATION DIAGRAM - MULTI CHIP CONFIGURATION 12A
FN7616 Rev 1.00
May 5, 2011
Page 5 of 22
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