CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32K/16K x 8, 32K x 9
Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
[1]
/15/20 ns
• Low operating power
— Active: I
CC
= 180 mA (typical)
— Standby: I
SB3
= 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
• Pb-Free packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
[2]
8/9
8/9
[2]
I/O
0L
–I/O
7/8L
I/O
Control
I/O
Control
I/O
0R
–I/O
7/8R
14/15
[4]
A
0L
–A
13/14L
Address
Decode
14/15
True Dual-Ported
RAM Array
Address
Decode
14/15
14/15
A
0R
–A
13/14R
[4]
[4]
A
0L
–A
13/14L
CE
L
OE
L
R/W
L
SEM
L
Interrupt
Semaphore
Arbitration
BUSY
L
INT
L
[3]
A
0R
–A
13/14R
CE
R
OE
R
R/W
R
SEM
R
[3]
[4]
BUSY
R
INT
R
M/S
Notes:
1. See page 7 for Load Conditions.
2. I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A
0
–A
13
for 16K; A
0
–A
14
for 32K devices.
Cypress Semiconductor Corporation
Document #: 38-06045 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 11, 2005
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations
68-Pin PLCC
Top View
SEM
L
R/W
L
A
14L
A
13L
[6]
NC(I/O
8L
[5]
)
OE
L
I/O
1L
I/O
0L
A
12L
A
11L
A
10L
CE
L
V
CC
A
9L
A
8L
A
7L
63
62
68
67
66
65
64
61
60
59
58
57
56
55
9
8
7
6
5
4
3
2
1
A
6L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O6
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
26
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
CY7C006A (16K x 8)
CY7C007A (32K x 8)
CY7C017A (32K x 9)
54
53
52
51
50
49
48
47
46
45
44
NC(I/O
8R
[5]
)
CE
R
A
14R
[6]
SEM
R
A
9R
A
8R
A
7R
A
8L
A
7L
64
GND
A
13R
A
12R
OE
R
R/W
R
I/O
7R
80-Pin TQFP
Top View
SEM
L
R/W
L
[6]
A
13L
I/O
1L
I/O
0L
A
12L
A
11L
OE
L
CE
L
NC
A
14L
A
10L
V
CC
A
11R
A
10R
A
9L
A
6L
80
79
78
77
NC
76
75
74
73
72
71
70
69
68
67
66
65
63
62
NC
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
NC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
1
2
3
4
5
6
7
8
61
NC
NC
A
6R
A
5R
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
NC
A
5R
CY7C007A (32K x 8)
CY7C016A (16K X 9)
R/W
R
SEM
R
I/O
7R
A
13R
CE
R
A
9R
A
8R
A
7R
GND
A
6R
NC
OE
R
A
12R
Notes:
5. This pin is I/O for CY7C017A only.
6. A
14
is a no connect pin for 16K devices.
Document #: 38-06045 Rev. *D
[6]
A
14R
A
11R
A
10R
NC
NC
40
41
Page 2 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations
(continued)
64-Pin TQFP
Top View
SEM
L
R/W
L
I/O
1L
I/O
0L
CE
L
A
13L
A
12L
A
11L
A
10L
OE
L
V
CC
A
9L
A
8L
52
A
7L
A
6L
A
5L
49
64
63
62
61
60
59
58
57
56
55
54
53
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
51
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
CY7C006A (16K x 8)
41
40
39
38
37
36
35
34
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
7R
R/W
R
SEM
R
I/O
6R
CE
R
A
13R
A
9R
A
8R
GND
A
12R
Selection Guide
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-12
[1]
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for I
SB1
(mA) (Both Ports TTL Level)
Typical Standby Current for I
SB3
(mA) (Both Ports CMOS Level)
12
195
55
0.05
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-15
15
190
50
0.05
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-20
20
180
45
0.05
Document #: 38-06045 Rev. *D
I/O
7R
A
11R
A
10R
OE
R
A
6R
A
5R
32
17
16
33
Page 3 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
14L
I/O
0L
–I/O
8L
SEM
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
CE
R
R/W
R
OE
R
A
0R
–A
14R
I/O
0R
–I/O
8R
SEM
R
INT
R
BUSY
R
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Bus Input/Output (I/O
0
–I/O
7
for x8 devices and I/O
0
–I/O
8
for x9)
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C006A, CY7C007A, and CY7C017A are available in
68-pin PLCC packages, the CY7C006A is also available in
64-pin TQFP, and the CY7C007A and CY7C016A are also
available in 80-pin TQFP packages.
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF) is the mailbox
for the right port and the second-highest memory location
(7FFE) is the mailbox for the left port. When one port writes to
Page 4 of 20
Description
Architecture
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
consist of an array of 32K/16K words of 8 bits and 32K words
of 9 bits each of dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two Interrupt
(INT) pins can be utilized for port-to-port communication. Two
Semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power-down
feature controlled by CE. Each port is provided with its own
Output Enable control (OE), which allows data to be read from
the device.
Functional Description
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
low-power CMOS 32K x 8/9 and 16K x 8/9 dual-port static
RAMs. Various arbitration schemes are included on the
devices to handle situations when multiple processors access
the same piece of data. Two ports are provided, permitting
independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
standalone 8/9-bit dual-port static RAMs or multiple devices
can be combined in order to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and
dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
Document #: 38-06045 Rev. *D
CY7C006A/CY7C007A
CY7C016A/CY7C017A
the other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. The operation of the interrupts and their interaction
with Busy are summarized in
Table 2.
Busy
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide on-chip arbitration to resolve simultaneous memory
location access (contention). If both ports’ CEs are asserted
and an address match occurs within t
PS
of each other, the busy
logic will determine which port has access. If t
PS
is violated,
one port will definitely gain permission to the location, but it is
not predictable which port will get that permission. BUSY will
be asserted t
BLA
after an address match or t
BLC
after CE is
taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (t
BLC
or t
BLA
),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For
example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be
deasserted for t
SOP
before attempting to read the semaphore.
The semaphore value will be available t
SWRD
+ t
DOE
after the
rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control of the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
0–2
represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
0
is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it.
Table 3
shows
sample semaphore operations.
When reading a semaphore, all data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within t
SPS
of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Document #: 38-06045 Rev. *D
Page 5 of 20
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