241/42
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
• High-speed, low-power, first-in, first-out (FIFO)
memories
• 64 x 9 (CY7C4421)
• 256 x 9 (CY7C4201)
• 512 x 9 (CY7C4211)
• 1K x 9 (CY7C4221)
• 2K x 9 (CY7C4231)
• 4K x 9 (CY7C4241)
• 8K x 9 (CY7C4251)
• High-speed 100-MHz operation (10 ns read/write cycle
time)
• Low power (I
CC
= 35 mA)
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independant read and write enable pins
• Center power and ground pins for reduced noise
• Width Expansion Capability
• Space saving 7mm x 7mm 32-pin TQFP
• 32-pin PLCC
• Pin compatible and functionally equivalent to IDT72421,
72201, 72211, 72221, 72231, 72241
Functional Description
THe CY7C42X1 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. The CY7C42X1 are pin-compatible to
IDT722X1. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and two write-en-
able pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
D0 - 8
INPUT
REGISTER
Pin Configuration
PLCC
Top View
4 3 2 1 32 31 30
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
141516 17 181920
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
D
2
D
3
D
4
D
5
D
6
D
7
D
8
FLAG
PROGRAM
REGISTER
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
EF
PAE
PAF
FF
D
2
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
42X1–2
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
WCLK WEN1 WEN2/LD
WRITE
CONTROL
TQFP
Top View
D
4
D
5
D
6
D
7
D
8
RS
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
42X1–3
OE
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
D
3
WRITE
POINTER
8k x 9
READ
POINTER
32 31 30 29 28 27 26 25
RS
RESET
LOGIC
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
1
2
3
4
5
6
7
8
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
THREE-ST
ATE
OUTPUTREGISTER
OE
Q0 - 8
READ
CONTROL
RCLK REN1 REN2
42X1–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
March 1995 - Revised September 30, 1997
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Functional Description
(continued)
The CY7C42X1 provides four status pins: Empty, Full, Almost Empty,
Almost Full. The Almost Empty/Almost Full flags are programmable
to single word granularity. The programmable flags default to
Empty – 7 and Full – 7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65µ
N-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
CY7C42X1-10
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
)
Commercial
Industrial
100
8
10
3
0.5
8
35
40
CY7C42X1-15
66.7
10
15
4
1
10
35
40
CY7C42X1-25
40
15
25
6
1
15
35
40
CY7C42X1-35
28.6
20
35
7
2
20
35
40
CY7C4421
Density
64 x 9
CY7C4201
256 x 9
CY7C4211
512 x 9
CY7C4221
1K x 9
CY7C4231
2K x 9
CY7C4241
4K x 9
CY7C4251
8K x 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ...................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied ...............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
[1]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V ± 10%
5V ± 10%
Note:
1. T
A
is the “instant on” case temperature.
2
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Pin Definitions
Signal Name
D
0–8
Q
0–8
WEN1
Description
Data Inputs
Data Outputs
Write Enable 1
I/O
I
O
I
Data Inputs for 9-bit bus
Data Outputs for 9-bit bus
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition
of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables the device for Read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off-
set register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed
into the FIFO.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Description
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
I
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I
I
RCLK
Read Clock
I
EF
FF
PAE
PAF
RS
OE
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
O
O
O
O
I
I
3
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Electrical Characteristics
Over the Operating Range
[2]
7C42X1-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OS[3]
I
OZL
I
OZH
I
CC1[4]
I
CC2[5]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Short
Circuit Current
Output OFF,
High Z Current
Active Power Supply
Current
Average Standby
Current
V
CC
= Max.
V
CC
= Max.,
V
OUT
= GND
OE > V
IH
,
V
SS
< V
O
< V
CC
Com’l
Ind
Com’l
Ind
Test Conditions
V
CC
= Min.,
I
OH
= –2.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
–3.0
–10
–90
–10
+10
35
40
10
15
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–3.0
–10
–90
–10
+10
35
40
10
15
Max.
7C42X1-15
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–3.0
–10
–90
–10
+10
35
40
10
15
Max.
7C42X1-25
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–3.0
–10
–90
–10
+10
35
40
10
15
Max.
7C42X1-35
Min.
2.4
0.4
V
CC
0.8
+10
Max.
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
Capacitance
[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
5
7
Unit
pF
pF
AC Test Loads and Waveforms
[7, 8]
R1 1.1KΩ
5V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉ VENIN EQUIVALENT
420Ω
OUTPUT
R2
680W
3.0V
GND
≤
3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤
3 ns
42X1–5
42X1–4
1.91V
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Test no more than one output at a time for not more than one second.
4. Outputs open. Tested at Frequency = 20 MHz.
5. All inputs = V
CC
– 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
6. Tested initially and after any design or process changes that may affect these parameters.
7. C
L
= 30 pF for all AC parameters except for t
OHZ
.
8. C
L
= 5 pF for t
OHZ
.
4
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Characteristics
Over the Operating Range
7C42X1-10
Parameter
t
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
SKEW1
t
SKEW2
Description
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width
[9]
Reset Set-Up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in High Z
[10]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag
5
10
[10]
7C42X1-15
Min.
2
15
6
6
4
1
4
1
15
10
10
Max.
66.7
10
7C42X1-25
Min.
2
25
10
10
6
1
6
1
25
15
15
Max.
40
15
7C42X1-35
Min.
2
35
14
14
7
2
7
2
35
20
20
Max.
28.6
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
0
3
3
15
15
20
20
20
20
12
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
2
10
4.5
4.5
3
0.5
3
0.5
10
8
8
Max.
100
8
10
0
3
3
7
7
8
8
8
8
6
15
0
3
3
15
0
8
8
10
10
10
10
10
18
3
3
25
12
12
15
15
15
15
Notes:
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
5
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