TSA1005
DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER
s
10-bit, dual-channel A/D converter in deep
s
Single supply voltage: 2.5V
s
s
s
s
s
submicron CMOS technology, 20/40Msps
GNDBE
VCCBE
REFPI
VCCBI
REFMI
VCCBI
INCMI
AVCC
AVCC
OEB
NC
NC
PIN CONNECTIONS
(top view)
Independent supply for CMOS output stage
with 2.5V/3.3V capability
ENOB=9.5 @ 20Msps, ENOB=9.2 @
40Msps, Fin=10MHz
SFDR typically up to 62.5dB @ 40Msps,
Fin=10MHz.
1GHz analog bandwidth Track-and-Hold
Common clocking between channels
Multiplexed outputs
index
corner
48 47 46 45
AGND 1
INI
2
44 43 42
41 40 39 38 37
36 D0(LSB)
35 D1
34 D2
33 D3
32 D4
31 D5
AGND 3
INIB 4
AGND 5
IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
13
14 15 16
17 18 19 20 21 22
23 24
TSA1005
30 D6
29 D7
28 D8
27 D9(MSB)
26 VCCBE
25 GNDBE
DESCRIPTION
The TSA1005 belongs to a new generation of high
speed, dual-channel Analog to Digital converters,
processed in a mainstream 0.25 µm CMOS tech-
nology and yielding high performances.
The TSA1005 is specifically designed for applica-
tions requiring a very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction,
providing high static linearity at 20/40 Msp, and
Fin = 10 MHz.
For each channel, a voltage reference is integrat-
ed to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC output is multiplexed on a common bus
with small number of pins. A tri-state capability is
available for the output signals, allowing for chip
selection. The input signals of the ADC must be
differentially driven.
The TSA1005 is supports an extended (0 to
+85°C) temperature range, and is available in the
small 48-pin TQFP package.
APPLICATIONS
BLOCK DIAGRAM
+2.5V/3.3V
CLK
SELECT
OEB
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
Timing
VINI
VINBI
VINCMI
VREFPI
VREFMI
IPOL
VREFPQ
VREFMQ
VINCMQ
VINQ
VINBQ
REF Q
REF I
AD 10
I channel
common mode
10
DGND
CLK
SELECT
Polar.
M
U
X
DGND
DVCC
GNDBI
VCCBE
10
10
Buffers
D0
TO
D9
common mode
AD 10
Q channel
10
s
s
s
s
s
Medical imaging and ultrasound
I/Q signal processing applications
High speed data acquisition system
Portable instrumentation
High resolution fax and scanners
GND
GNDBE
ORDER CODE
Part Number
TSA1005-20IF
TSA1005-20IFT
TSA1005I-40IF
TSA1005-40IFT
EVAL1005-20/BA
EVAL1005-40/BA
Temperature
Range
-40°C to +85°C
-40°C to +85°C
0°C to +85°C
0°C to +85°C
Status
Sample
Sample
Production
Production
Evaluation board
Conditioning
Tray
Tape & Reel
Tray
Tape & Reel
PACKAGE
7
×
7 mm TQFP48
June 2003
1/22
TSA1005
ABSOLUTE MAXIMUM RATINGS
Symbol
AVCC
DVCC
VCCBE
VCCBI
IDout
Tstg
ESD
Analog Supply voltage
(1)
Digital Supply voltage
1)
Digital buffer Supply voltage
1)
Digital buffer Supply voltage
1)
Digital output current
Storage temperature
HBM: Human Body Model
(2)
CDM: Charged Device Model
(3)
Parameter
Values
0 to 3.3
0 to 3.3
0 to 3.6
0 to 3.3
-100 to 100
+150
2
1.5
A
Unit
V
V
V
V
mA
°C
kV
Latch-up Class
(4)
1 All voltage values, except for differential voltage, are with respect to the network ground terminal. The magnitude of input and output volt-
ages must not exceed -0.3 V or VCC
2 ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ
3 Discharge to Ground of a device that has been previously charged.
4 Corporate ST Microelectronics procedure number 0018695
OPERATING CONDITIONS
Symbol
AVCC
DVCC
VCCBE
VCCBI
VREFPI
VREFPQ
VREFMI
VREFMQ
INCMI
INCMQ
Parameter
Analog Supply voltage
Digital Supply voltage
External Digital buffer Supply voltage
Internal Digital buffer Supply voltage
Forced top voltage reference
Forced bottom reference voltage
Forced input common mode voltage
TSA1005-20
(1)
Min.
2.25
2.25
2.25
2.25
0.94
0
0.2
Typ.
2.5
2.5
2.5
2.5
Max.
2.7
2.7
3.5
2.7
1.4
0.4
1
Min.
2.25
2.25
2.25
2.25
0.94
0
0.2
TSA1005-40
Typ.
2.5
2.5
2.5
2.5
Max.
2.7
2.7
3.5
2.7
1.4
0.4
1
Unit
V
V
V
V
V
V
V
2/22
TSA1005
PIN CONNECTIONS
(top view)
GNDBE
VCCBE
REFPI
VCCBI
VCCBI
REFMI
INCMI
AVCC
AVCC
OEB
NC
NC
index
corner
48
AGND 1
INI
2
47 46 45
44 43 42
41 40 39 38 37
36 D0(LSB)
35 D1
34 D2
33 D3
32 D4
31 D5
AGND 3
INIB 4
AGND 5
IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
13
14 15 16
17 18 19 20 21 22 23 24
TSA1005
30 D6
29 D7
28 D8
27 D9(MSB)
26 VCCBE
25 GNDBE
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
DGND
CLK
SELECT
DGND
DVCC
GNDBI
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
AGND
INI
AGND
INBI
AGND
IPOL
AVCC
AGND
INQ
AGND
INBQ
AGND
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
DGND
CLK
SELECT
DGND
DVCC
GNDBI
Description
Analog ground
I channel analog input
Analog ground
I channel inverted analog input
Analog ground
Analog bias current input
Analog power supply
Analog ground
Q channel analog input
Analog ground
Q channel inverted analog input
Analog ground
Q channel top reference voltage
Q channel bottom reference
voltage
Q channel input common mode
Analog ground
Analog power supply
Digital power supply
Digital ground
Clock input
Channel selection
Digital ground
Digital power supply
Digital buffer ground
0V
2.5V
2.5V
0V
2.5V CMOS input
2.5V CMOS input
0V
2.5V
0V
0V
0V
0V
2.5V
0V
0V
0V
0V
Observation
Pin No
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
GNDBE
VCCBE
D9(MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0(LSB)
NC
NC
VCCBE
GNDBE
VCCBI
VCCBI
OEB
AVCC
AVCC
INCMI
REFMI
REFPI
Description
Digital buffer ground
Digital Buffer power supply
Most Significant Bit output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Least Significant Bit output
Non connected
Non connected
Digital Buffer power supply
Digital buffer ground
Digital Buffer power supply
Digital Power Supply
Output Enable input
Analog power supply
Analog power supply
I channel input common mode
I channel bottom reference voltage 0V
I channel top reference voltage
2.5V/3.3V - See Application
Note
0V
2.5V
2.5V
2.5V/3.3V CMOS input
2.5V
2.5V
0V
2.5V/3.3V
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
Observation
3/22
TSA1005
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5 V, Fs = 20/40 Msps, Fin = 10.13 MHz, Vin@ -1 dBFS, VREFP = 0.8 V,
VREFM = 0 V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
TSA1005-20
(1)
Symbol
FS
DC
TC1
TC2
Tod
Tpd I
Tpd Q
Ton
Toff
Parameter.
Min.
Sampling Frequency
Clock Duty Cycle
Clock pulse width (high)
Clock pulse width (low)
Data Output Delay (Clock edge to Data
Valid) - 10pF load capacitance
Data Pipeline delay for I channel
Data Pipeline delay for Q channel
Falling edge of OEB to digital output
valid data
Rising edge of OEB to digital output
tri-state
0.5
50
25
25
5
7
7.5
1
1
Typ.
Max.
20
Min.
0.5
45
50
12.5
12.5
5
7
7.5
1
1
Typ.
Max.
40
55
Unit
MHz
%
ns
ns
ns
cycles
cycles
ns
ns
TSA1005-40
1 Preliminary data.
TIMING DIAGRAM
Simultaneous sampling
on I/Q channels
N+3
N+4
N+5
N+6
N+12
N+13
I
N-1
N
Q
N+1
N+2
N+7
N+8
N+9
N+10
N+11
CLK
Tpd I + Tod
Tod
SELECT
CLOCK AND SELECT CONNECTED TOGETHER
OEB
sample N-8
I channel
sample N-6
Q channel
sample N
Q channel
sample N+1
Q channel
sample N+2
Q channel
DATA
OUTPUT
sample N-9
I channel
sample N-7
Q channel
sample N+1 sample N+2
I channel
I channel
sample N+3
I channel
4/22
TSA1005
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol
VIN-VINB
Cin
Req
BW
ERB
Parameter
Full scale reference voltage
Input capacitance
Equivalent input resistor
Analog Input Bandwidth
Vin Full scale, Fs max
Effective Resolution Bandwidth
1.1
TSA1005-20
(1)
Min.
Typ.
2.0
7.0
3.3
1000
70
Max.
2.8
Min.
1.1
TSA1005-40
Typ.
2.0
7
1.6
1000
70
Max.
2.8
Unit
Vpp
pF
KΩ
MHz
MHz
1 Preliminary data
DIGITAL INPUTS AND OUTPUTS
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
Clock and Select inputs
VIL
VIH
OEB input
VIL
VIH
Logic "0" voltage
Logic "1" voltage
0
0.75 x VCCBE
VCCBE
Iol=10µA
Ioh=10µA
0.1 x
VCCBE
0.25 x
VCCBE
V
V
Logic "0" voltage
Logic "1" voltage
2.0
0
2.5
0.8
V
V
Digital Outputs
VOL
VOH
IOZ
C
L
Logic "0" voltage
Logic "1" voltage
0
0.9 x VCCBE
VCCBE
-1.67
0
V
V
1.67
15
µA
pF
High Impedance leakage current OEB set to VIH
Output Load Capacitance
REFERENCE VOLTAGE
Symbol
VREFPI
VREFPQ
VINCMI
VINCMQ
Parameter
TSA1005-20
(1)
Min.
Top internal reference voltage
Input common mode voltage
0.81
0.41
Typ.
0.88
0.46
Max.
0.94
0.50
Min.
0.81
0.41
TSA1005-40
Typ.
0.88
0.46
Max.
0.94
0.50
Unit
V
V
5/22
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