Si554
Q
U A D
F
R E Q U E N C Y
VCXO (10 MH
Z T O
1.4 GH
Z
)
Features
Available with any-rate output
frequencies from 10–945 MHz and
select frequencies to 1.4 GHz
Four selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL, LVDS
& CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Applications
SONET/SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical Modules
Clock and data recovery
Ordering Information:
See page 7.
Description
The Si554 quad frequency VCXO utilizes Silicon Laboratories advanced
DSPLL
®
circuitry to provide a very low jitter clock for all output frequencies.
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and select frequencies to 1400 MHz. Unlike traditional VCXOs where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
FS[1]
7
V
C
1
2
3
8
FS[0]
6
5
4
V
DD
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK- CLK+
FS1
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
®
Clock Synthesis
FS0
ADC
V
c
OE
GND
Rev. 0.5 7/06
Copyright © 2006 by Silicon Laboratories
Si554
Si554
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
TriState mode
Output Enable (OE)
and Frequency Select FS[1:0]
2
Operating Temperature Range
3
T
A
V
IH
V
IL
Min
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
120
108
99
90
60
—
—
—
Max
3.63
2.75
1.89
130
117
108
98
70
—
0.5
85
V
ºC
V
Units
mA
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2.
OE and FS[1:0] pins include a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.
3.
If the device is powered up below –20 ºC and the ambient temperature rises by approximately 105 ºC during normal
operation, the device will perform a one-time recalibration. The output is squelched for approximately 2–3 ms during
this recalibration.
Table 2. V
C
Control Voltage Input
Parameter
Control Voltage Tuning Slope
1,2,3
Symbol
K
V
Test Condition
10 to 90% of V
DD
Min
—
Typ
45
90
135
180
±1
±5
10.0
—
3/8 x V
DD
Max
—
Units
ppm/V
Control Voltage Linearity
4
Modulation Bandwidth
V
C
Input Impedance
Nominal Control Voltage
Control Voltage Tuning Range
L
VC
BW
Z
VC
V
CNOM
V
C
BSL
Incremental
–5
–10
9.3
500
+5
+10
10.7
—
—
V
DD
%
kHz
kΩ
V
V
@ f
O
—
0
Notes:
1.
Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 7.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
K
V
variation is ±28% of typical values.
4.
BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.
2
Rev. 0.5
Si554
Table 3. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2,3
Temperature Stability
1,4
Symbol
f
O
∆f/f
O
Test Condition
LVDS/CML/LVPECL
CMOS
T
A
= –40 to +85 ºC
Min
10
10
–20
–50
–100
±25
Frequency drift over 15
year life.
t
OSC
Typ
—
—
—
—
—
—
—
—
—
Max
945
160
+20
+50
+100
±150
±10
10
20
Units
MHz
ppm
ppm
ppm
ms
ms
Absolute Pull Range
1,4
Aging
Power up Time
5
Settling Time After FS[1:0] Change
APR
—
—
t
FRQ
Both FS[1] and FS[0]
changing simultaneously
—
Notes:
1.
See Section 3. "Ordering Information" on page 7 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Nominal output frequency set by V
CNOM
= 3/8 x V
DD
.
4.
Selectable parameter specified by part number.
5.
Time from power up or tristate mode to f
O
(to within ±1 ppm of f
O
).
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.5
1.125
0.32
Typ
—
Max
V
DD
– 1.25
1.9
0.93
1.275
0.50
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.40
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
CMOS Output Option
3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
V
O
V
OD
V
OH
V
OL
t
R,
t
F
mid-level
swing
(diff)
I
OH
= 32 mA
I
OL
= 32 mA
—
0.70
0.8 x V
DD
V
DD
– 0.75
0.95
—
—
—
1
—
—
1.20
V
DD
V
V
PP
V
—
—
—
45
0.4
350
—
55
LVPECL/LVDS/CML
CMOS with CL = 15 pF
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
ps
ns
%
SYM
Notes:
1.
50
Ω
to V
DD
– 2.0 V.
2.
R
term
= 100
Ω
(differential).
3.
C
L
= 15 pF
Rev. 0.5
3
Si554
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1,2,3
for F
OUT
> 500 MHz
Symbol
Test Condition
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Phase Jitter (RMS)
1,2,3
for F
OUT
of 125 to 500 MHz
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
0.35
0.38
0.43
0.41
0.52
0.46
0.64
0.52
0.42
0.58
0.48
0.60
0.57
0.64
0.67
0.68
Max
—
—
—
—
—
—
—
—
ps
—
—
—
—
—
—
—
—
Units
ps
φ
J
φ
J
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Notes:
1.
Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
for F
OUT
< 160 MHz
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
2
14
Max
—
—
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
4
Rev. 0.5
Si554
Table 7. CLK± Output Phase Noise (Typical)
Configuration
f
C
K
V
Output
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
–94
–117
–128
–135
–138
–143
n/a
74.25 MHz
45 ppm/V
CMOS
L
(f)
–74
–98
–112
–122
–134
–144
–147
–77
–101
–114
–118
–128
–144
–147
300 MHz
90 ppm/V
LVPECL
622.08 MHz
45 ppm/V
LVPECL
Units
dBc/Hz
Table 8. Absolute Maximum Ratings
1
Parameter
Supply Voltage
Input Voltage (any input pin)
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
Symbol
V
DD
V
I
T
S
ESD
T
PEAK
t
P
Rating
–0.5 to +3.8
–0.5 to V
DD
+ 0.3
–55 to +125
>2500
260
10
Units
Volts
Volts
ºC
Volts
ºC
seconds
Notes:
1.
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
2.
Refer to Si5xx Packaging FAQ available for download from
www.silabs.com/VCXO
for further information, including
soldering profiles.
Table 9. Environmental Compliance
The Si554 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Conditions/ Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Rev. 0.5
5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
