Revision 5
Radiation-Tolerant ProASIC3 Low Power Spaceflight
Flash FPGAs with Flash*Freeze Technology
Features and Benefits
MIL-STD-883 Class B Qualified Packaging
• Ceramic Column Grid Array with Six Sigma Copper-Wrapped
Lead-Tin Columns
• Land Grid Array
• Ceramic Quad Flat Pack
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced and Pro (Professional) I/Os
•
•
•
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, and 3.3 V PCI / 3.3 V PCI-X
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (RT3PE3000L only)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay (RT3PE3000L only)
Schmitt Trigger Option on Single-Ended Inputs (RT3PE3000L)
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the Radiation-Tolerant (RT)
ProASIC
®
3 Family
Low Power
• Dramatic Reduction in Dynamic and Static Power
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
• Low Power Consumption in Flash*Freeze Mode
Radiation Performance
• 25 Krad to 30 Krad with 10% Propagation Delay Increase
(TM 1019 Cond. A, Dose Rate 5 Krad/min)
• Up to 40 Krad with 10% Propagation Delay Increase, Dose Rate
< 1 Krad/min
• Up to 55 Krad with 15% Propagation Delay Increase, Dose
Rate < 1 Krad/min
• Wafer-Lot-Specific TID Reports
High Capacity
• 600 k to 3 M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, All with Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
High Performance
• 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V)
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
In-System Programming (ISP) and Security
• True Dual-Port SRAM (except ×18)
• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES)
• 24 SRAM and FIFO Blocks with Synchronous Operation:
Decryption via JTAG (IEEE 1532–compliant)
– 250 MHz: For 1.2 V Systems
• FlashLock
®
Designed to Secure FPGA Contents
– 350 MHz: For 1.5 V Systems
Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low Power Spaceflight FPGAs
RT ProASIC3 Devices
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
CCGA/LGA
CQFP
RT3PE600L
600,000
13,824
108
24
1
Yes
6
18
8
270
CG/LG484
CQ256
RT3PE3000L
3,000,000
75,264
504
112
1
Yes
6
18
8
620
CG/LG484, CG/LG896
CQ256
September 2012
© 2012 Microsemi Corporation
I
ProASIC3 nano Flash FPGAs
I/Os Per Package
1
RT ProASIC3 Low Power Devices
Package
CG/LG484
CG/LG896
CQ256
RT3PE600L
Single-Ended I/Os
270
–
166
2
RT3PE3000L
Single-Ended I/Os
341
620
166
2
Differential I/O Pairs
135
–
82
Differential I/O
Pairs
168
310
82
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to
ensure you are complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For RT3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V / GTL 2.5 V: up to 72 I/Os per north or south bank
4. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended
user I/Os available is reduced by one.
RT ProASIC3 Device Status
RT ProASIC3 Devices
RT3PE600L
RT3PE3000L
Status
Production
Production
II
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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs
RT ProASIC3 Ordering Information
RT3PE3000L _
1
CG
484
Y
B
Application (Screening Level)
B = MIL-STD-883 Class B
E = Extended Flow
PROTO = Protoype Unit; Not for Space-Flight or Qualification of
Space-Flight Hardware
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Package Type
CG = Ceramic Column Grid Array (1.0 mm pitch)
LG = Land Grid Array (1.0 mm pitch)
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
Part Number
RT ProASIC3 Spaceflight FPGAs
RT3PE600L = 600,000 System Gates
RT3PE3000L = 3,000,000 System Gates
Screening Levels
Package
CG/LG484
CG/LG896
CQ256
Note:
B = MIL-STD-883 Class B screening
E = Extended flow
PROTO = Prototype unit; not for space-flight or qualification of space-flight hardware.
RT3PE600L
B, E, PROTO
–
B, E, PROTO
RT3PE3000L
B, E, PROTO
B, E, PROTO
B, E, PROTO
Speed Grade Offerings
Speed Grade
Std.
–1
RT3PE600L
RT3PE3000L
✓
✓
✓
✓
Notes:
1. Data applies to B, E, and PROTO flow devices.
2. Contact your local
Microsemi SoC Products Group representative
for availability.
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III
ProASIC3 nano Flash FPGAs
MIL-STD-883 Class B Product Flow
Table 2 • MIL-STD-883 Class B Product Flow for RT ProASIC3 Devices*
Step
1
2
3
4
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
1010, Condition C, 10 cycles minimum
2001, Y1 Orientation Only
Condition B for CQ256, CQ352, LG624, LG1152
Condition D for CQ208
Condition A for LG1272, LGD1272, CQ352
2020, Condition A
1014
In accordance with applicable Microsemi device
specification
1015, Condition D,
160 hours at 125°C or 80 hours at 150°C minimum
In accordance with applicable Microsemi device
specification
5%
In accordance with applicable Microsemi device
specification, which includes a, b, and c:
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
Screen
2010, Condition B
Method
Requirement
100%
100%
100%
100%
5
6
7
8
9
10
11
Particle Impact Noise Detection
Seal (Fine & Gross Leak Test)
Pre-Burn-In Electrical Parameters
Dynamic Burn-In
Interim (Post-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
a. Static Tests
(1) 25°C
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
(2) –55°C and +125°C
c. Switching Tests at 25°C
100%
100%
100%
100%
100%
All Lots
100%
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
5005, Table 1, Subgroup 9
2009
12
External Visual
100%
Note:
*For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical
visual are performed after solder column attachment.
IV
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Radiation-Tolerant ProASIC3 Low Power Spaceflight Flash FPGAs
Extended Flow (E Flow)
Table 3 • Extended Flow for RT ProASIC3 Devices
1,2
Step
1
2
3
4
5
6
7
8
9
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Radiographic (X-Ray)
Pre-Burn-In Test
Dynamic Burn-In
1010, Condition C
2001, Condition B or D, Y1 Orientation Only
2020, Condition A
2012, One View (Y1 Orientation) Only
In accordance with applicable Microsemi device specification
1015, Condition D, 240 hours at 125°C or 120 hours at 150°C
minimum
1015, Condition C, 72 hours at 150°C or 144 hours at 125°C
minimum
5%, 3% Functional Parameters at 25°C
In accordance with Microsemi applicable device specification
which includes a, b, and c:
5005
5005
100%
5005
5005
100%
5005
1014
100%
Screen
Destructive In-Line Bond Pull
3
2011, Condition D
2010, Condition A
Method
Requirement
Sample
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
All Lots
100%
100%
10 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device specification
11
Static Burn-In
12 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device specification
13 Percent Defective Allowable (PDA)
Calculation
14 Final Electrical Test
a. Static Tests
(1) 25°C
(Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table 15)
(2) –55°C and +125°C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
15 Seal
a. Fine
b. Gross
16 External Visual
2009
100%
Notes:
1. Microsemi offers Extended Flow for users requiring additional screening beyond MIL-STD-883, Class B requirement. Microsemi
offers this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883,
Class S. The exceptions to Method 5004 are shown in notes 2 and 4 below.
2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual
are performed after solder column attachment.
3. Method 5004 requires a 100 percent, nondestructive bond-pull to Method 2003. Microsemi substitutes a destructive bond-pull
to Method 2011 Condition D on a sample basis only.
4. MIL-STD-883, Method 5004, requires a 100 percent radiation latch-up testing to Method 1020. Microsemi will NOT perform any
radiation testing, and this requirement must be waived in its entirety.
5. Wafer lot acceptance complies to commercial standards only (requirement per Method 5007 is not performed).
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