Revision 9
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Designed for Space
• SEU-Hardened Registers Eliminate the Need to Implement
Triple-Module Redundancy (TMR)
– Immune to Single Event Upsets (SEU) to LET
th
> 40 MeV-
cm
2
/mg,
– SEU Rate < 10
–10
Upset/Bit-Day in Worst-Case
Geosynchronous Orbit
• Up to 100 krad (Si) Total Ionizing Dose (TID)
– Parametric Performance Supported with Lot-Specific Test
Data
• Single-Event Latch-Up (SEL) Immunity to LET
TH
> 104
MeVcm2/mg
• TM1019.5 Test Data Available
• QML Certified Devices
Specifications
•
•
•
•
0.25 µm Metal-to-Metal Antifuse Process (UMC)
48,000 to 108,000 Available System Gates
Up to 2,012 SEU-Hardened Flip-Flops
Up to 360 User-Programmable I/O Pins
Features
• Very Low Power Consumption (Up to 68 mW at Standby)
• 3.3 V and 5 V Mixed Voltage
• Configurable I/O Support for 3.3 V/5 V PCI, LVTTL, TTL, and
CMOS
– 5 V Input Tolerance and 5 V Drive Strength
– Slow Slew Rate Option
– Configurable Weak Resistor Pull-Up/Down for Tristated
Outputs at Power-Up
– Hot-Swap Compliant with Cold-Sparing Support
• Secure Programming Technology Designed to Protect Against
Reverse Engineering and Design Theft
• 100% Circuit Resource Utilization with 100% Pin Locking
• Unique In-System Diagnostic and Verification Capability with
Silicon Explorer II
• Deterministic, User-Controllable Timing
• JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 – Dedicated JTAG Reset (TRST) Pin
High Performance
• 230 MHz System Performance
• 310 MHz Internal Performance
• 9.5 ns Input Clock to Output Pad
Processing Flows
• B-Flow – MIL-STD-883B
• E-Flow – Extended Flow
• EV-Flow – Class V Equivalent Flow Processing Consistent with
MIL-PRF 38535
Prototyping Options
• Commercial SX-A Devices for Functional Verification
• RTSX-SU PROTO Devices with Same Functional and Timing
Characteristics as Flight Unit in a Non-Hermetic Package
Table 1 • RTSX-SU Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
SEU-Hardened Register Cells (Dedicated Flip-Flops)
Maximum Flip-Flops
Maximum User I/Os
Clocks
Quadrant Clocks
Speed Grades
Package
(by pin count)
CQ
CG
CC
RTSX32SU
32,000
48,000
2,880
1,800
1,080
1,980
227
3
0
Std., –1
84, 208, 256
256
RTSX72SU
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Std., –1
208, 256
624
March 2012
© 2012 Microsemi Corporation
i
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Ordering Information
RTSX72SU
1
CQ
256
B
Application (T emperature Range)
B = MIL-STD-883 Class B
E = E-Flow (Space Level Flow)
M = Military Temperature
EV = Class V Equivalent Flow Processing
Consistent with MIL-PRF-38535
PROTO = Prototyping Flow
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
CG = Ceramic Column Grid Aray
CC = Ceramic Chip Carrier Land Grid
Speed Grade
Blank =
Standard Speed
1 =
Approximately 15% Faster than Standard
Part Number
RTSX32SU
=
32,000 RadTolerant Typical Gates
RTSX72SU
=
72,000 RadTolerant Typical Gates
RTSX-SU Device Status
RTSX-SU Devices
RTSX32SU
RTSX72SU
Status
Production
Production
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R ev i si o n 9
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Ceramic Device Resources
User I/Os (including clock buffers)
Device
RTSX32SU
RTSX72SU
CQ84
62
–
CQ208
173
170
CQ256
227
212
CC256
202
–
CG624
–
360
Temperature Grade and Application Offering
Package
CQ84
CQ208
CQ256
CC256
CG624
RTSX32SU
B, E, EV, PROTO
B, E, EV, PROTO
B, E, EV, PROTO
M, B, E, EV, PROTO
–
RTSX72SU
–
B, E, EV, PROTO
B, E, EV, PROTO
–
B, E, EV, PROTO
Note:
M = Military Temperature
B = MIL-STD-883 Class B
E = E-Flow
EV = Microsemi SoC Products Group V Equivalent Flow (Class V Processing Consistent with MIL-PRF-38535)
PROTO = RTSX-SU prototype units.
Speed Grade and Temperature Grade Matrix
RTSX32SU
STD
–1
RTSX72SU
✓
✓
✓
✓
Notes:
1. Data applies to M, B, E, EV, and PROTO flow devices.
2. Contact your Microsemi SoC Products Group representative for availability.
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iii
RTSX-SU Radiation-Tolerant FPGAs (UMC)
QML Certification
Microsemi has achieved full QML certification, demonstrating that quality management procedures, processes, and controls are in
place and comply with MIL-PRF-38535 (the performance specification used by the U.S. Department of Defense for monolithic
integrated circuits).
MIL-STD-883 Class B Product Flow
Table 2 • MIL-STD-883 Class B Product Flow* for RTSX32SU and RTSX72SU
Step
1
2
3
4
5
Internal Visual
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Seal
a. Fine
b. Gross
Visual Inspection
Pre-Burn-In
Electrical Parameters
Dynamic Burn-In
Interim (Post-Burn-In)
Electrical Parameters
Percent Defective Allowable
Final Electrical Test
a. Static Tests
(1) 25°C
(Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2, 3, Table I)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table I)
(2) –55°C and +125°C
(Subgroups 8A and 8B, Table
I)
c. Switching Tests at 25°C
(Subgroup 9, Table I)
External Visual
Screen
2010, Test Condition B
1010, Test Condition C
2001, Test Condition B or D, Y
1
, Orientation Only
2020, Condition A
1014
100%
100%
2009
In accordance with applicable Microsemi
device specification
1015, Condition D,
160 hours at 125°C or 80 hours at 150°C
In accordance with applicable Microsemi
device specification
5%
In accordance with applicable Microsemi
device specification, which includes a, b, and
5005
5005
100%
5005
5005
100%
5005
2009
100%
100%
100%
100%
100%
All Lots
100%
883 Method
883–Class B
Requirement
100%
100%
100%
100%
6
7
8
9
10
11
12.
Note:
*For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical
visual are performed after solder column attachment.
iv
R ev i si o n 9
RTSX-SU Radiation-Tolerant FPGAs (UMC)
Extended Flow
Table 3 • Extended Flow for RTSX32SU and RTSX72SU
1,2
Step
1
2
3
4
5
6
7
8
9
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Radiographic (X-Ray)
6
Pre-Burn-In Test
Dynamic Burn-In
1010, Condition C
2001, Condition B or D, Y1 Orientation Only
2020, Condition A
2012, One View (Y1 Orientation) Only
In accordance with applicable Microsemi device specification
1015, Condition D, 240 hours at 125°C or 120 hours at 150°C
minimum
1015, Condition C, 72 hours at 150°C or 144 hours at 125°C
minimum
5%, 3% Functional Parameters at 25°C
In accordance with Microsemi applicable device specification
which includes a, b, and c:
5005
5005
100%
5005
5005
100%
5005
1014
100%
Screen
Destructive In-Line Bond Pull
3
2011, Condition D
2010, Condition A
Method
Requirement
Sample
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
All Lots
100%
100%
10 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device specification
11
Static Burn-In
12 Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Microsemi device specification
13 Percent Defective Allowable (PDA)
Calculation
14 Final Electrical Test
a. Static Tests
(1) 25°C
(Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table 15)
(2) –55°C and +125°C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
15 Seal
a. Fine
b. Gross
16 External Visual
2009
100%
Notes:
1. Microsemi offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Microsemi
offers this Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883,
Class S. The exceptions to Method 5004 are shown in notes 2 and 4 below.
2. For CCGA devices, all Assembly/Screening/TCI testing are performed at LGA level. Only QA electrical and mechanical visual
are performed after solder column attachment.
3. Method 5004 requires a 100 percent, nondestructive bond-pull to Method 2003. Microsemi substitutes a destructive bond-pull
to Method 2011 Condition D on a sample basis only.
4. MIL-STD-883, Method 5004, requires a 100 percent radiation latch-up testing to Method 1020. Microsemi will NOT perform any
radiation testing, and this requirement must be waived in its entirety.
5. Wafer lot acceptance complies to commercial standards only (requirement per Method 5007 is not performed).
6. X-Ray inspection is not performed on RTSX72SU in CQ208 and CQ256 packages because these packages contain a heat-
spreader that prevents the X-Rays from penetrating through.
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FPGA/CPLD
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