Advanced v0.3
™
u e
RTSX-SU RadTolerant FPGAs (UMC)
Designed for Space
•
SEU-Hardened Registers Eliminate the Need to
Implement Triple-Module Redundancy (TMR)
– Immune to Single-Event Upsets (SEU) to LET
th
> 40 MeV-cm
2
/mg,
– SEU Rate < 10
–10
Upset/Bit-Day in Worst-Case
Geosynchronous Orbit
Up to 100 krad (Si) Total Ionizing Dose (TID)
– Parametric Performance Supported with Lot-
Specific Test Data
Single-Event Latch-Up (SEL) Immunity
TM1019.5 Test Data Available
QML Certified Devices
Features
•
•
•
Very Low Power Consumption (Up to 68 mW at
Standby)
3.3V and 5V Mixed Voltage
Configurable I/O Support for 3.3V/5V PCI, LVTTL,
TTL, and CMOS
– 5V Input Tolerance and 5V Drive Strength
– Slow Slew Rate Option
– Configurable Weak Resistor Pull-Up/Down for
Tristated Outputs at Power-Up
– Hot-Swap
Compliant
with
Cold-Sparing
Support
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
100% Circuit Resource Utilization with 100% Pin
Locking
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low-Cost Prototyping Option
Deterministic, User-Controllable Timing
JTAG Boundary Scan Testing in Compliance with
IEEE Standard 1149.1 – Dedicated JTAG Reset
(TRST) Pin
•
•
•
•
•
•
•
•
•
•
High Performance
•
•
•
230 MHz System Performance
310 MHz Internal Performance
9.5 ns Input Clock to Output Pad
Specifications
•
•
•
•
0.25 µm Metal-to-Metal Antifuse Process (UMC)
48,000 to 108,000 Available System Gates
Up to 2,012 SEU-Hardened Flip-Flops
Up to 360 User-Programmable I/O Pins
Table 1 •
RTSX-SU Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
SEU-Hardened Register Cells (Dedicated Flip-Flops)
Maximum Flip-Flops
Maximum User I/Os
Clocks
Quadrant Clocks
Speed Grades
Package
(by pin count)
CQFP
CCGA
CCLG
RTSX32SU
32,000
48,000
2,880
1,800
1,080
1,980
227
3
0
Std., –1
208, 256
256
RTSX72SU
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Std., –1
208, 256
624
October 2004
© 2004 Actel Corporation
i
See Actel’s website for the latest version of the datasheet
RTSX-SU RadTolerant FPGAs (UMC)
Ordering Information
RTSX72SU
1
CQ
256
B
Application (Temperature Range)
B = MIL-STD-883 Class B
E = E-Flow (Actel Space Level Flow)
M = Military Temperature
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
CG = Ceramic Column Grid Aray
CC = Ceramic Chip Carrier Land Grid
Speed Grade
Blank = Standard Speed
1 = Approximately 15% Faster than Standard
Part Number
RTSX32SU
=
32,000 RadTolerant Typical Gates
RTSX72SU
=
72,000 RadTolerant Typical Gates
Ceramic Device Resources
User I/Os (including clock buffers)
Device
RTSX32SU
RTSX72SU
Note:
The 256-Pin CCLG available in Mil-Temp only.
CQFP
208-Pin
173
170
CQFP
256-Pin
227
212
CCLG
256-Pin
202
–
CCGA
624-Pin
–
360
Temperature Grade and Application Offering
Package
CQ208
CQ256
CC256
CG624
Note:
M = Military Temperature
B = MIL-STD-883 Class B
E = E-Flow
RTSX32SU
B, E
B, E
M
–
RTSX72SU
B, E
B, E
–
B, E
ii
A d v a n c e d v 0 .3
RTSX-SU RadTolerant FPGAs (UMC)
Speed Grade and Temperature/Application Matrix
Std.
M
B
E
✓
✓
✓
-1
✓
✓
✓
QML Certification
Actel has achieved full QML certification, demonstrating that quality management procedures, processes, and controls
are in place and comply with MIL-PRF-38535 (the performance specification used by the U.S. Department of Defense
for monolithic integrated circuits).
Actel MIL-STD-883 Class B Product Flow
Step
1.
2.
3.
4.
5.
Internal Visual
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Seal
a. Fine
b. Gross
Visual Inspection
Pre-Burn-In
Electrical Parameters
Dynamic Burn-In
Interim (Post-Burn-In)
Electrical Parameters
Percent Defective Allowable
Final Electrical Test
a. Static Tests
(1)25°C
(Subgroup 1, Table I)
(2)–55°C and +125°C
(Subgroups 2, 3, Table I)
b. Functional Tests
(1)25°C
(Subgroup 7, Table I)
(2)–55°C and +125°C
(Subgroups 8A and 8B, Table I)
c. Switching Tests at 25°C
(Subgroup 9, Table I)
12.
External Visual
Screen
883 Method
2010, Test Condition B
1010, Test Condition C
2001, Test Condition B or D,
Y
1
, Orientation Only
2020, Condition A
1014
100%
100%
2009
In accordance with applicable Actel
device specification
1015, Condition D,
160 hours at 125°C or 80 hours at 150°C
In accordance with applicable Actel
device specification
5%
In accordance with applicable Actel
device specification, which includes a, b, and c:
100%
5005
5005
100%
5005
5005
100%
5005
2009
100%
100%
100%
100%
100%
All Lots
883–Class B
Requirement
100%
100%
100%
100%
6.
7.
8.
9.
10.
11.
A d v a n c ed v 0.3
iii
RTSX-SU RadTolerant FPGAs (UMC)
Actel Extended Flow
1
Step
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Radiographic
Pre-Burn-In Test
Dynamic Burn-In
Interim (Post-Burn-In) Electrical Parameters
Static Burn-In
Interim (Post-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA)
Calculation
Final Electrical Test
a. Static Tests
(1)25°C
(Subgroup 1, Table1)
(2)–55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1)25°C
(Subgroup 7, Table 15)
(2)–55°C and +125°C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
15.
Seal
a. Fine
b. Gross
External Visual
1010, Condition C
2001, Condition B or D, Y
1
Orientation Only
2020, Condition A
2012 (one view only)
In accordance with applicable Actel device specification
1015, Condition D, 240 hours at 125°C or 120 hours at
150°C minimum
In accordance with applicable Actel device specification
1015, Condition C, 72 hours at 150°C or 144 hours at
125°C minimum
In accordance with applicable Actel device specification
5%, 3% Functional Parameters at 25°C
In accordance with Actel applicable device specification
which includes a, b, and c:
5005
5005
100%
5005
5005
100%
5005
1014
100%
Screen
Destructive In-Line Bond Pull
3
2011, Condition D
2010, Condition A
Method
Requirement
Sample
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
All Lots
100%
100%
16.
Notes:
2009
100%
1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Actel offers this
Extended Flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The
exceptions to Method 5004 are shown in notes 2 and 4 below.
2. MIL-STD-883, Method 5004, requires a 100 percent radiation latch-up testing to Method 1020. Actel will NOT perform any
radiation testing, and this requirement must be waived in its entirety.
3. Method 5004 requires a 100 percent, nondestructive bond-pull to Method 2003. Actel substitutes a destructive bond-pull to
Method 2011 Condition D on a sample basis only.
4. Wafer lot acceptance complies to commercial standards only (requirement per Method 5007 is not performed).
iv
A d v a n c e d v 0 .3
RTSX-SU RadTolerant FPGAs (UMC)
Table of Contents
General Description
Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Low-Cost Prototyping Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Detailed Specification
General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Package Pin Assignments
208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
256-Pin CCLG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
624-Pin CCGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
A dv an ce d v 0. 3
v
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
