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SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES516G – DECEMBER 2003 – REVISED FEBRUARY 2006
FEATURES
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.65-V to
5.5-V Power-Supply Range
V
CC
Isolation Feature – If Either V
CC
Input Is at
GND, Both Ports Are in the High-Impedance
State
DIR Input Circuit Referenced to V
CCA
Low Power Consumption, 10-µA Max I
CC
±24-mA
Output Drive at 3.3 V
I
off
Supports Partial-Power-Down Mode
Operation
Max Data Rates
– 420 Mbps (3.3-V to 5-V Translation)
– 210 Mbps (Translate to 3.3 V)
– 140 Mbps (Translate to 2.5 V)
– 75 Mbps (Translate to 1.8 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
•
V
CCA
A1
A2
GND
1
2
3
4
8
7
6
5
V
CCB
B1
B2
DIR
•
•
•
•
•
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND
A2
A1
V
CCA
D1
C1
B1
A1
4 5
3
6
D2
C2
B2
A2
DIR
B2
B1
V
CCB
2 7
1 8
•
•
DESCRIPTION/ORDERING INFORMATION
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track V
CCA
. V
CCA
accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track
V
CCB
. V
CCB
accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
SSOP – DCT
VSSOP – DCU
(1)
(2)
ORDERABLE PART NUMBER
SN74LVC2T45YEPR
Reel of 3000
SN74LVC2T45YZPR
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
SN74LVC2T45DCTR
SN74LVC2T45DCTT
SN74LVC2T45DCUR
SN74LVC2T45DCUT
CT2_ _ _
CT2_
_ _ _TB_
TOP-SIDE MARKING
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES516G – DECEMBER 2003 – REVISED FEBRUARY 2006
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data
from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the
A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess I
CC
and I
CCZ
.
The SN74LVC2T45 is designed so that the DIR input circuit is supplied by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, both ports are in the high-impedance state.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
(1)
(EACH TRANSCEIVER)
INPUT
DIR
L
H
(1)
OPERATION
B data to A bus
A data to B bus
Input circuits of the data I/Os
always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
5
A1
2
7
B1
A2
3
6
B2
V
CCA
V
CCB
2
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www.ti.com
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES516G – DECEMBER 2003 – REVISED FEBRUARY 2006
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CCA
V
CCB
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Voltage range applied to any output in the high or low state
(2) (3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
DCT package
θ
JA
T
stg
(1)
(2)
(3)
(4)
Package thermal
impedance
(4)
DCU package
YEP/YZP package
Storage temperature range
–65
A port
B port
V
I
< 0
V
O
< 0
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
6.5
6.5
6.5
V
CCA
+ 0.5
V
CCB
+ 0.5
–50
–50
±50
±100
220
227
102
150
°C
°C/W
UNIT
V
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of V
CC
is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SN74LVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES516G – DECEMBER 2003 – REVISED FEBRUARY 2006
www.ti.com
Recommended Operating Conditions
(1) (2) (3)
V
CCI
V
CCA
V
CCB
Supply voltage
1.65 V to 1.95 V
V
IH
High-level
input voltage
Data inputs
(4)
2.3 V to 2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 1.95 V
V
IL
Low-level
input voltage
Data inputs
(4)
2.3 V to 2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 1.95 V
V
IH
High-level
input voltage
DIR
(referenced to V
CCA
)
(5)
2.3 V to 2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 1.95 V
V
IL
Low-level
input voltage
DIR
(referenced to V
CCA
)
(5)
2.3 V to 2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
V
I
V
O
Input voltage
Output voltage
1.65 V to 1.95 V
I
OH
High-level output current
2.3 V to 2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 1.95 V
I
OL
Low-level output current
2.3 V to 2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 1.95 V
∆t/∆v
Input transition
rise or fall rate
Data inputs
2.3 V to 2.7 V
3 V to 3.6 V
4.5 V to 5.5 V
Control input
T
A
(1)
(2)
(3)
(4)
(5)
Operating free-air temperature
1.65 V to 5.5 V
–40
0
0
V
CCA
×
0.65
1.7
2
V
CCA
×
0.7
V
CCA
×
0.35
0.7
0.8
V
CCA
×
0.3
5.5
V
CCO
–4
–8
–24
–32
4
8
24
32
20
20
10
5
5
85
°C
ns/V
mA
mA
V
V
V
V
V
CCO
MIN
1.65
1.65
V
CCI
×
0.65
1.7
2
V
CCI
×
0.7
V
CCI
×
0.35
0.7
0.8
V
CCI
×
0.3
V
V
MAX
5.5
5.5
UNIT
V
V
CCI
is the V
CC
associated with the input port.
V
CCO
is the V
CC
associated with the output port.
All unused data inputs of the device must be held at V
CCI
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
For V
CCI
values not specified in the data sheet, V
IH
min = V
CCI
×
0.7 V, V
IL
max = V
CCI
×
0.3 V.
For V
CCI
values not specified in the data sheet, V
IH
min = V
CCA
×
0.7 V, V
IL
max = V
CCA
×
0.3 V.
4
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