TBB1008
Twin Build in Biasing Circuit MOS FET IC
VHF/UHF RF Amplifier
ADE-208-1599 (Z)
Rev.0
Jun. 2002
Features
•
Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.
•
Suitable for World Standard Tuner RF amplifier.
•
Very useful for total tuner cost reduction.
•
Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 200 V at C = 200 pF, Rs = 0
conditions.
•
Provide mini mold packages; CMPAK-6
Outline
CMPAK-6
6
5
4
2
1
3
1. Gate-1(1)
2. Source
3. Drain(1)
4. Drain(2)
5. Gate-2
6. Gate-1(2)
Notes:
1.
2.
Marking is “HM”.
TBB1008 is individual type number of HITACHI TWIN BBFET.
TBB1008
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate1 to source voltage
Gate2 to source voltage
Drain current
Channel power dissipation
Channel temperature
Storage temperature
Symbol
V
DS
V
G1S
V
G2S
I
D
Pch
Tch
Tstg
*3
Ratings
6
+6
-0
+6
-0
30
250
150
–55 to +150
Unit
V
V
V
mA
mW
°C
°C
Notes: 3. Value on the glass epoxy board (50 mm
×
40 mm
×
1 mm).
Rev.0, Jun. 2002, page 2 of 12
TBB1008
Electrical Characteristics
The below specification are applicable for UHF unit (FET1)
(Ta = 25°C)
Item
Drain to source breakdown
voltage
Gate1 to source breakdown
voltage
Gate2 to source breakdown
voltage
Symbol Min
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
6
+6
+6
—
—
0.5
0.5
13
21
1.4
1.0
—
16
Typ
—
—
—
—
—
0.7
0.7
17
26
1.8
1.4
0.02
21
Max
—
—
—
+100
+100
1.0
1.0
21
32
2.2
1.8
0.04
—
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
pF
dB
Test Conditions
I
D
= 200
µA,
V
G1S
= V
G2S
= 0
I
G1
= +10
µA,
V
G2S
= V
DS
= 0
I
G2
= +10
µA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V, I
D
= 100
µA
V
DS
= 5 V, V
G1S
= 5 V, I
D
= 100
µA
V
DS
= 5 V, V
G1
= 5 V
V
G2S
= 4 V, R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V
V
G2S
=4 V, R
G
= 100 kΩ
f = 1 MHz
V
DS
= V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 900 MHz
Zi = S11*, Zo = S22* (:PG)
Zi = S11opt (:NF)
Gate1 to source cutoff current I
G1SS
Gate2 to source cutoff current I
G2SS
Gate1 to source cutoff voltage V
G1S(off)
Gate2 to source cutoff voltage V
G2S(off)
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
I
D(op)
|y
fs
|
Ciss
Coss
Crss
PG
Noise figure
NF
—
1.7
2.5
dB
Rev.0, Jun. 2002, page 3 of 12
TBB1008
The below specification are applicable for VHF unit (FET2)
(Ta = 25°C)
Item
Drain to source breakdown
voltage
Gate1 to source breakdown
voltage
Gate2 to source breakdown
voltage
Symbol Min
V
(BR)DSS
V
(BR)G1SS
V
(BR)G2SS
6
+6
+6
—
—
0.5
0.5
16
27
2.3
1.4
—
24
—
Typ
—
—
—
—
—
0.75
0.75
20
32
2.7
1.8
0.03
29
1.2
Max
—
—
—
+100
+100
1.0
1.0
24
38
3.1
2.2
0.05
—
1.7
Unit
V
V
V
nA
nA
V
V
mA
mS
pF
pF
pF
dB
dB
Test Conditions
I
D
= 200
µA,
V
G1S
= V
G2S
= 0
I
G1
= +10
µA,
V
G2S
= V
DS
= 0
I
G2
= +10
µA,
V
G1S
= V
DS
= 0
V
G1S
= +5 V, V
G2S
= V
DS
= 0
V
G2S
= +5 V, V
G1S
= V
DS
= 0
V
DS
= 5 V, V
G2S
= 4 V, I
D
= 100
µA
V
DS
= 5 V, V
G1S
= 5 V, I
D
= 100
µA
V
DS
= 5 V, V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ
V
DS
= 5 V, V
G1
= 5 V, V
G2S
=4 V
R
G
= 100 kΩ, f = 1 kHz
V
DS
= 5 V, V
G1
= 5 V
V
G2S
=4 V, R
G
= 100 kΩ
f = 1 MHz
V
DS
= V
G1
= 5 V, V
G2S
= 4 V
R
G
= 100 kΩ, f = 200 MHz
Gate1 to source cutoff current I
G1SS
Gate2 to source cutoff current I
G2SS
Gate1 to source cutoff voltage V
G1S(off)
Gate2 to source cutoff voltage V
G2S(off)
Drain current
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Noise figure
I
D(op)
|y
fs
|
Ciss
Coss
Crss
PG
NF
Rev.0, Jun. 2002, page 4 of 12
TBB1008
Test Circuits
•
DC Biasing Circuit for Operating Characteristic Items
(I
D(op)
, |yfs|, Ciss, Coss, Crss, NF, PG)
•
Measurment of FET1
Gate 2
V
G2
Open
Open
R
G
V
G1
Gate 1
Source
Drain
A
I
D
V
D
•
Measurment of FET2
V
G2
Gate 2
R
G
V
G1
Gate 1
Drain
A
I
D
V
D
Open
Source
Open
Rev.0, Jun. 2002, page 5 of 12
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