MwT-LN240
26 GHz Super Low Noise pHEMT Device
May 2010
FEATURES
0.5 dB Minimum Noise Figure at 12 GHz
10 dB Associated Gain at 12 GHz
16 dBm P1dB at 12 GHz
0.15 Micron x 240 Micron Gate
APPLICATIONS
Excellent Choice for Super Low Noise Applications
Ideal for Commercial, Military, Hi-Rel Space Applications
DESCRIPTION
The MwT- LN240 is a super low noise, quasi-enhancement-mode pHEMT whose nominal 0.15 micron gate length and
240 micron gate width makes it ideally suited for applications requiring very low noise figure and high associated gain
up to 30 GHz. The device is equally effective for wideband (e.g. 6 to 18 GHz) and narrow-band applications. Each wafer
can be screened to meet high quality and reliability requirements for military and space applications.
RF SPECIFICATIONS AT Ta = 25 C
S YM BOL
NF m in
SSG
P 1dB
P ARAM ETERS & CONDITIONS
M inim um Nois e Figure
V ds = 2.5V Ids = 20 m A (V gs = 0)
A s s oc iated Gain
V ds = 2.5V Ids = 20 m A (V gs = 0)
Output P ower at 1dB Com pres s ion
V ds = 3.0V Ids = 50 m A
FREQ
4 GHz
12 GHz
4 GHz
12 GHz
12 GHz
UNITS
dB
dB
dB m
M IN
TYP
0.2
0.5
13
10
16.0
M AX
Note: MWT-LN240 is a quas i enhanc ement mode dev ic e. For bes t nois e f igure, V gs bias v oltage s hould be s et at
either 0 or s lightly pos itiv e v oltages to ac hiev e the target operating c urrent.
DC SPECIFICATIONS AT Ta = 25 C
S YM BOL
Im a x
Gm
Vp
BV GS O
BV GDO
Rth *
P ARAM ETERS & CONDITIONS
S aturated Drain Current
V ds = 2.5V V gs = 0.6V
Trans c onduc tanc e
V ds = 2.5V V gs = 0.2V
P inc h-off V oltage
V ds = 2.0V Ids = 0.5m A
Gate-to-S ourc e B reak down V oltage
Igs = -0.3m A
Gate-to-Drain B reak down V oltage
Igd = -0.3m A
Chip Therm al Res is tanc e
FREQ
UNITS
mA
mS
V
V
V
ºC/W
-6.0
-7.5
140
M IN
TYP
110
180
-0.2
-8.0
-9.0
300
M AX
* Ov erall Rth depends on c hip mounting
4268 Solar Way
Fremont, CA 94538
sales@mwtinc.com
P (510) 651-6700
F (510) 952-4000
www.mwtinc.com
MwT-LN240
26 GHz Super Low Noise pHEMT Device
May 2010
NOISE PARAMETERS Vds=2.5V, Ids=20mA
S-PARAMETERS V=2.5V, Ids=20mA
Gold Block
10X10X5
2 places
Chip Dimensions: 410 x 430 microns
Source pad: 80 x 280
Gate and Drain pad: 90 x 90
Chip Thickness: 100 microns
RECOMMENDED ASSEMBLY CONFIGURATION
Bond Wire
1.0 mil die
10 places
Note: The gold blocks and circuits should be
placed as close to the device as possible. The
bond wire should be as short as possible.
MAXIMUM RATINGS at Ta = 25 C
Sym bol
VDS
Tch
Tst
Pin
Param e te rs
Drain to Source Voltage
Channel Temperature
Storage Temperature
RF Input Pow er
Units
V
ºC
ºC
mW
Cont
M ax 1
4.0
+150
-65 to +160
16
Abs olute
M ax 2
4.5
+175
+180
30
Pt
Total Pow er Dissipation
mW
300
400
Exceeding any on of these limits in continuous operation may reduce the
mean-time-to-f ailure below the design goal and may cause permanent damage
4268 Solar Way
Fremont, CA 94538
sales@mwtinc.com
P (510) 651-6700
F (510) 952-4000
www.mwtinc.com
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