SRAM
MT5C6405
16K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-86859
• MIL-STD-883
PIN ASSIGNMENT
(Top View)
24-Pin DIP (C)
(300 MIL)
A5
A6
A7
A8
A9
A10
A11
A12
A13
CE\
OE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
FEATURES
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
28-Pin LCC (EC)
A5
NC
NC
Vcc
NC
3 2 1 28 27
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (300 mil) C
Ceramic LCC
MARKING
-12
-15
-20
-25
-35
-45*
-55*
-70*
A6 4
A7 5
A8 6
A9 7
A10 8
A11 9
A12 10
A13 11
CE\ 12
26
25
24
23
22
21
20
19
18
NC
A4
A3
A2
A1
A0
DQ4
DQ3
DQ2
13 14 15 16 17
DQ1
WE\
NC
Vss
OE\
No. 106
EC
No. 204
GENERAL DESCRIPTION
The Micross Components SRAM family employs high-
speed, low-power CMOS designs using a four-transistor mem-
ory cell. Austin Semiconductor SRAMs are fabricated using
double-layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Micross
Components offers chip enable (CE\) and output enable (OE\)
capability. These enhancements can place the outputs in High-Z
for additional flexibility in system design.
Writing to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished
when WE\ remains HIGH and CE\ and OE\ go LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power
requirements.
All devices operate from a single +5V power supply and all
inputs and outputs are fully TTL compatible.
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 35ns ac-
cess devices.
For more products and information
please visit our web site at
www.miross.com
MT5C6405
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
1
SRAM
MT5C6405
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
A
A
A
A
A
A
A
A
A
D
ROW DECODER
I/O CONTROL
Q
1,048,576-BIT
MEMORY ARRAY
CE\
(LSB)
OE\
COLUMN DECODER
POWER
DOWN
WE\
(LSB)
A A A A A A A A A A
TRUTH TABLE
MODE
STANDBY
READ
READ
WRITE
OE\
X
L
H
X
CE\
H
L
L
L
WE\
X
H
H
L
DQ
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
MT5C6405
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
2
SRAM
MT5C6405
*Stresses greater than those listed under “Absolute Maximum
ABSOLUTE MAXIMUM RATINGS*
1
Voltage on any Input or DQ Relative to Vss....-0.5V to +7.0V Ratings” may cause permanent damage to the device. This
Storage Temperature…...................................-65
o
C to +150
o
C is a stress rating only and functional operation of the device
Power Dissipation.................................................................1W at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
Max Junction Temperature..................................................+175°C
o
Lead Temperature (soldering 10 seconds)........................+260 C to absolute maximum rating conditions for extended periods
Short Circuit Output Current...........................................20mA may affect reliability.
1 All voltage referenced to Vss.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V < V
IN
< V
CC
Outputs Disabled
0V < V
OUT
< V
CC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
SYM
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MIN
2.2
-0.5
-10
-10
2.4
0.4
MAX
-20
110
MAX
Vcc+0.5V
0.8
10
10
UNITS NOTES
V
V
μA
μA
V
V
1
1
1
1, 2
PARAMETER
Power Supply
Current: Operating
Power Supply
Current: Standby
CONDITIONS
CE\ < V
IL
; V
CC
= MAX
Output Open
CE\ > V
IH
; V
CC
= MAX
f = 0 Hz
CE\ > (V
CC
-0.2); V
CC
= MAX
All Other Inputs < 0.2V
or > (V
CC
- 0.2V), f = 0 Hz
SYM
I
cc
-12
140
-15
125
-25
100
-35
90
UNITS NOTES
mA
3
I
SBT1
50
45
40
35
30
mA
I
SBC2
25
25
25
25
25
mA
CAPACITANCE
DESCRIPTION
Input Capacitance
Output Capacitance
CONDITIONS
T
A
= 25 C, f = 1MHz
Vcc = 5V
o
SYM
C
I
C
O
MAX
8
10
UNITS
pF
pF
NOTES
4
4
MT5C6405
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
3
SRAM
MT5C6405
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-12
-15
-20
-25
-35
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
SYMBOL
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
12
12
12
2
2
7
0
12
6
0
6
12
10
10
0
0
10
7
0
2
0
15
12
12
0
0
12
8
0
2
0
0
7
20
15
15
0
0
15
10
0
2
0
0
15
7
0
8
25
20
20
0
0
20
12
0
2
0
2
2
8
0
20
8
0
10
35
25
25
0
0
25
15
0
2
0
15
15
15
2
2
10
0
25
10
8
15
20
20
20
2
2
12
0
35
15
25
25
25
2
2
15
35
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6, 7
6
6
7
8
10
15
7
6, 7
MT5C6405
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
4
SRAM
MT5C6405
+5V
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
+5V
480
480
Q
255
5 pF
Q
255
30pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF
as in Fig. 2. Transition is measured ±200mV typical from
steady state voltage, allowing for actual tester RC time con-
stant.
1.
2.
3.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
t
11. RC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The waveform
is inverted.
7.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
- 0.2V)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
1
mA
CONDITIONS
SYM
V
DR
MIN
2
MAX
---
UNITS
V
NOTES
t
CDR
t
R
0
t
RC
---
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
4.5V
V > 2V
DR
t
R
V
DR
CE\
V
IH
V
IL
DON’T CARE
UNDEFINED
MT5C6405
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
