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CMOS Static RAM
256K (32K x 8-Bit)
IDT71256SA
x
x
Features
32K x 8 advanced high-speed CMOS static RAM
Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
Equal access and cycle times
– Commercial and Industrial: 12/15/20/25ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Commercial product available in 28-pin 300- and 600-mil
Plastic DIP, 300 mil Plastic SOJ and TSOP packages
Industrial product available in 28-pin 300 mil Plastic SOJ
and TSOP packages
Description
The IDT71256SA is a 262,144-bit high-speed Static RAM organized
as 32K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with
innovative circuit design techniques, provides a cost-effective solution for
high-speed memory needs.
The IDT71256SA has an output enable pin which operates as fast as
6ns, with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71256SA are TTL-compatible and operation is from a
single 5V supply. Fully static asynchronous circuitry is used, requiring no
clocks or refresh for operation.
The IDT71256SA is packaged in 28-pin 300- and 600-mil Plastic DIP,
28-pin 300 mil Plastic SOJ and TSOP.
x
x
x
x
x
x
Functional Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
ADDRESS
DECODER
262,144-BIT
MEMORY
ARRAY
,
I/O
0 -
I/O
7
8
8
I/O CONTROL
2948 drw 01
CS
WE
OE
CONTROL
LOGIC
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-2948/07
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Absolute Maximum Ratings
(1)
Symbol
Rating
Supply Voltage
Relative to GND
Terminal Voltage
Relative to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7.0
-0.5 to V
CC
+0.5
-55 to +125
-55 to +125
1.0
50
Unit
V
V
o
SO28-5
P28-2
P28-1
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
2948 drw 02
V
CC
V
TERM
T
BIAS
T
STG
P
T
I
OUT
C
C
o
W
mA
2948 tbl 02
,
DIP/SOJ
Top View
OE
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
SO28-8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
Truth Table
(1,2)
CS
L
OE
L
X
H
X
X
WE
H
L
H
X
X
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Outputs Disabled
Deselected - Standby (I
SB
)
Deselecte d - Standby (I
SB1
)
2948 tbl 03
,
L
L
H
V
HC
(3)
2948 drw 02a
TSOP
Top View
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
–0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
4.5V ± 5.5V
4.5V ± 5.5V
2948 tbl 01
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
V
CC
+0.5
0.8
Unit
V
V
V
V
2948 tbl 04
____
NOTE:
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
2
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
IDT71256SA
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= Max., V
IN =
GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= -4mA, V
CC
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2948 tbl 05
2.4
DC Electrical Characteristics
(1)
Symbol
I
CC
I
SB
I
SB1
Parameter
Dynamic Operating Current
CS
< V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
> V
IH
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (CMOS Level)
CS
> V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
,
V
IN
< V
LC
or V
IN
> V
HC
(V
CC
= 5.0V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
0.2V)
71256SA12
160
50
15
71256SA15
150
40
15
71256SA20
145
40
15
71256SA25
145
40
15
Unit
mA
mA
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
2948 tbl 06
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
2948 tbl 07
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
2948 tbl 08
Capacitance
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
5V
480Ω
DATA
OUT
30pF*
255Ω
2948 drw 03
5V
480Ω
DATA
OUT
5pF*
255Ω
,
6.42
3
.
2948 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol
Parameter
(V
CC
= 5.0V ± 10%)
71256SA12
Min.
Max.
71256SA15
Min.
Max.
71256SA20
Min.
Max.
71256SA25
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Select to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disab le to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
12
____
____
15
____
____
20
____
____
25
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
____
15
15
____
20
20
____
25
25
____
____
____
____
____
4
0
____
4
0
____
4
0
____
4
0
____
6
6
____
7
7
____
10
10
____
11
11
____
0
0
3
0
____
0
0
3
0
____
0
0
3
0
____
0
0
3
0
____
6
____
6
____
8
____
10
____
____
____
____
____
12
15
20
25
Write Cycle
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Output Active from End-of-Write
Write Enab le to Output in High-Z
12
9
9
0
8
0
6
0
4
0
____
____
____
____
____
____
____
____
15
10
10
0
10
0
7
0
4
0
____
____
____
____
____
____
____
____
20
15
15
0
15
0
11
0
4
0
____
____
____
____
____
____
____
____
25
20
20
0
20
0
13
0
4
0
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2948 tbl 09
____
____
____
____
6
6
10
11
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
4
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