CY101E383
ECL/TTL/ECL Translator
and High-Speed Bus Driver
Features
• BiCMOS for optimum speed/power
• High speed (max.)
— 3.0 ns t
PD
TTL-to-ECL
•
•
•
•
•
•
•
•
•
•
— 4 ns t
PD
ECL-to-TTL
Low skew <
±
1 ns
Can operate on single +5V supply
Full-duplex ECL/TTL data transmission
Internal 2 kΩ ECL pull-down resistors on each ECL
output
80-pin PQFP package
84-pin PLCC package
V
BB
ECL reference voltage output
Single- or dual-supply operation
Capable of greater than 2001V ESD
ECL cable/twisted pair driver
mance systems. The device contains ten independent
TTL-to-ECL and ten independent ECL-to-TTL translators for
high-speed full-duplex data transmission, mixed logic, and bus
applications. The CY101E383 is especially suited to drive ECL
backplanes between TTL boards. The CY101E383 is imple-
mented with differential ECL I/O to provide balanced low noise
operation over controlled impedance buses between TTL
and/or ECL subsystems. In addition, the device has internal
output 2 kΩ pull-down resistors tied to VEE to decrease the
number of external components. For system testing pur-
poses or for driving light loads, the 2 kΩ is used as the only
termination thereby eliminating up to 20 external resistors.
The part meets standard 100K logic levels with the internal
pull-down while driving 50Ω to
−2V.
The device is designed with ample ground pins to reduce
bounce, and has separate ECL and TTL power/ground pins to
reduce noise coupling between logic families. The parts can
operate in single- or dual-supply configurations while main-
taining absolute and 100K level swings. The translators are
offered in a standard 100K ECL-compatible version with
−5.2V
or
−4.5V
power supply. The TTL I/O is fully TTL compatible.
The CY101E383 is packaged in 84-pin surface-mountable
PLCCs and CLCCs. To save board space, an 80-pin PQFP
package with 25-mil-lead pitch is available.
Functional Description
The CY101E383 is a new-generation TTL-to-ECL and
ECL-to-TTL logic level translator designed for high-perfor-
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
July 1990 - Revised April 11, 1997
CY101E383
Logic Block Diagram
VBB
D0
D0
DIFFERENTIAL D1
ECL INPUTS D1
ECL SUPPL D2
Y
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D11
D12
D13
D14
TTL INPUTS D15
TTL SUPPLY
D16
D17
D18
D19
ECL D4
ECL D4
ECL D3
ECL D3
ECL D2
ECL D2
ECL D1
ECL D1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
Q14
Q14
Q15 DIFFERENTIAL
Q15
Q16 ECL OUTPUTS
Q16 ECL SUPPLY
Q17
Q17
Q18
Q18
Q19
Q19
10
5
7
1
TTL OUTPUTS
TTL SUPPLY
ECL D5
ECL D5
ECL D6
ECL D6
ECL D7
ECL D7
ECL D8
ECL D8
ECL D9
ECL D9
ECL VBB
ECL VCC
ECL Q10
ECL Q10
ECL VCC
ECL Q11
ECL Q11
ECL VCC
ECL Q12
ECL Q12
ECL VCC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Pin Configurations
PLCC/CLCC
Top View
ECL D0
ECL D0
TTL VCC
TTL Q9
TTL GND
TTL Q7
TTL GND
TTL Q6
TTL VCC
TTL Q5
TTL GND
TTL VCC
TTL Q8
11 10 9
8 7 6
5
4 3 2
1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
TTL GND
TTL Q4
TTL VCC
TTL Q3
TTL GND
TTL Q2
TTL VCC
TTL Q1
TTL GND
TTL Q0
TTL GND
TTL D19
TTL D18
TTL D17
TTL D16
TTL D15
TTL D14
TTL D13
TTL D12
TTL D11
TTL D10
101E383
65
64
63
62
61
60
59
58
57
30
56
31
55
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
ECL Q13
ECL Q13
ECL VEE
ECL Q14
ECL Q14
ECL Q15
ECL Q15
ECL VCC
ECL Q16
ECL Q16
ECL VCC
ECL Q17
ECL Q17
ECL Q18
ECL Q18
ECL VCC
ECL Q19
ECL VCC
ECL Q19
ECL VCC
TTL GND
Note 1
Note:
1.
The PQFP package has one less each TTL V
CC
and TTL GND pin and two less ECL V
CC
pins.
ECL VCC
TTL VCC
ECL VEE
E383-1
ECL VCC
E383-2
2
CY101E383
Pin Configurations
(continued)
PQFP
Top View
ECL D0
ECL D0
TTL VCC
TTL Q9
TTL GND
TTL GND
TTL Q6
TTL VCC
TTL Q5
TTL GND
ECL D4
ECL D4
ECL D3
ECL D3
ECL D2
ECL D2
ECL D1
ECL D1
TTL Q8
TTL Q7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
ECL D5
ECL D5
ECL D6
ECL D6
ECL D7
ECL D7
ECL D8
ECL D8
ECL D9
ECL D9
ECL VBB
ECL VCC
ECL Q10
ECL Q10
ECL VCC
ECL Q11
ECL Q11
ECL Q12
ECL Q12
ECL VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
60
59
58
57
56
55
54
TTL Q4
TTL VCC
TTL Q3
TTL GND
TTL Q2
TTL VCC
TTL Q1
TTL GND
TTL Q0
TTL GND
TTL D19
TTL D18
TTL D17
TTL D16
TTL D15
TTL D14
TTL D13
TTL D12
TTL D11
TTL D10
101E383
53
52
51
50
49
48
47
46
45
44
43
19
42
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
ECL Q13
ECL Q13
ECL VEE
ECL Q14
ECL Q14
ECL Q15
ECL Q15
ECL Q16
ECL Q16
ECL VCC
ECL Q17
ECL Q17
ECL Q18
ECL Q18
ECL VCC
ECL Q19
ECL VCC
ECL VCC
ECL Q19
ECL VCC
E383-3
Selection Guide
101E383−3
Maximum Propagation Delay Time (ns) (TTL to ECL)
Maximum Propagation Delay Time (ns) (ECL to TTL)
Maximum Operating Current (mA) Sum of I
EE
and I
CC
3
4
300
ECL Output Current
.........................................................−50
mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied
.................................................. −55°C
to +125°C
TTL Supply Voltage to Ground Potential
.........−0.5V
to +7.0V
TTL DC Input Voltage
.........................................−3.0V
to +7.0V
ECL Supply Voltage V
EE
to ECL V
CC
..............−7.0V
to +0.5V
ECL Input Voltage ............................................. V
EE
to +0.5V
Operating Range
Range
I/O
Ambient
Version Temperature
101E
ECL
V
EE
TTL
V
CC
0
°
C to +85
°
C
−4.2Vto
5V
±
−5.46V
5%
Commercial 100K
3
CY101E383
ECL Electrical Characteristics
Over the Operating Range
[2]
101E383
Parameter
V
OH
V
OL
V
IH
V
IL
V
BB
V
CM[5]
V
DIFF
I
IH
I
IL
R
PD
I
EE
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Output Reference Voltage
Common Mode Voltage
Input Voltage Differential
Input HIGH Current
Input LOW Current
Pull-Down Resistor
Supply Current (All inputs
and outputs open)
Test Conditions
101E, R
L
= 50Ω to
−2V
V
IN
= V
IH
Min. or V
IL
Max.
101E, R
L
= 50Ω to
−2V
V
IN
= V
IH
Min. or V
IL
Max.
101E
101E
101E
[4]
±V
CM
with respect to V
BB
Required for Full Output Swing
V
IN
= V
IH
Max.
V
IN
= V
IL
Min.
Connected from All ECL Out-
puts to V
EE
T
A
= 0°C to 85°C
−0.5
1.6
150
220
170
3.0
−180
Temperature
[3]
T
A
= 0°C to 85°C
T
A
= 0°C to 85°C
T
A
= 0°C to 85°C
T
A
= 0°C to 85°C
T
A
= 0°C to 85°C
Min.
−1065
−1900
−1165
−1900
−1.5
Max.
−700
−1600
−700
−1475
−1.15
1.0
Unit
mV
mV
mV
mV
V
V
mV
µA
µA
kΩ
mA
TTL Electrical Characteristics
Over the Operating Range
[2]
101E383
Parameter
V
OH
V
OL
V
IH
V
IL
V
CD
I
OS[7]
I
IX
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
[6]
Input LOW Voltage
[5]
Input Clamp Diode Voltage
Output Short-Circuit Current
Input Load Current
[9]
V
CC
Operating Supply Current
I
IN
=
−10
mA
V
CC
= Max., V
OUT
= 0.5V
[8]
GND < V
I
< V
CC
V
CC
= Max., I
OUT
= 0 mA, f = f max.
−1.5
−180
−250
−40
+20
120
Test Conditions
V
CC
= Min., I
OH
=
−3.2
mA
V
CC
= Max., I
OL
= 16.0 mA
2.0
0.8
Min.
2.4
0.5
Max.
Unit
V
V
V
V
V
mA
µA
mA
Capacitance
[7]
Parameter
C
IN[7]
C
OUT[7]
Description
Input Capacitance
Output Capacitance
Max.
4
5
Unit
pF
pF
Notes:
2. See AC Test Load and Waveform for test conditions.
3. Commercial grade is specified as ambient temperature with transverse air flow greater than 500 linear feet per minute.
4. Max. I
BB
=
−1
mA.
5. The internal gain of the CY101E383 guarantees that the output voltage will not change for common mode signals to
±1V.
Therefore, input C
MRR
is infinite within the
common mode range.
6. These are absolute values with respect to device ground.
7. Characterized initially and after any design or process changes that may affect these parameters.
8. Not more than one output should be tested at a time. Duration of the short should not be more than one second.
9. I/O pin leakage is the worst case of I
IX
(where X = H or L).
4
CY101E383
TTL AC Test Load and Waveform
[10]
5V
OUTPUT
C
L
pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2170
Ω
(236Ω MIL)
E383-5
R1238Ω (319Ω MIL)
3.0V
GND
≤
3 ns
90%
10%
90%
10%
≤
3 ns
E383-4
THÉ
VENIN EQUIVALENT (Commercial)
OUTPUT
99Ω
2.08V
THÉVENIN EQUIVALENT (Military)
OUTPUT
136Ω
2.13V
thm
ECL AC Test Load and Waveform
[11, 12, 13, 14, 15]
GND
ALL INPUT PULSES
V
CC
, V
CCO
INPUT
D
OUT
V
EE
0.01
µF
V
EE
R
L
−2.0V
E383-6
E383-7
V
IH
V
IL
20%
80%
80%
20%
C
L
t
r
t
f
ECL-to-TTL Switching Characteristics
Over the Operating Range
101E383−3
Parameter
t
PLH
t
PHL
Description
Propagation Delay Time
Propagation Delay Time
Test Conditions
D
n
, D
n
to Q
n
D
n
, D
n
to Q
n
Min.
1
1
Max.
4
4
Unit
ns
ns
TTL-to-ECL Switching Characteristics
Over the Operating Range
101E383−3
Parameter
t
PLH
t
PHL
t
R[7]
t
R[7]
Description
Propagation Delay Time
Propagation Delay Time
Output Rise Time
Output Fall Time
Test Conditions
D
n
to Q
n
, Q
n
D
n
to Q
n
, Q
n
20% to 80%
20% to 80%
Min.
1
1
0.35
0.35
Max.
3
3
1.7
1.7
Unit
ns
ns
ns
ns
Skew Time Switching Characteristics
[7]
(Same test conditions as TTL-to-ECL and ECL-to-TTL Electrical Characteristics)
Symbol
t
SKT[7]
t
SKE[7]
Characteristic
Data Skew Time ECL-to-TTL
Data Skew Time TTL-to-ECL
Test Conditions
TTLQ
n
to TTLQ
n+m
ECLQ
n
, Q
n
to ECLQ
n+m
, Q
n+m
Min.
Max.
1
1
Unit
ns
ns
5
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