FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/20/25
PALCE22V10 Family
24-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
s
As fast as 5-ns propagation delay and
142.8 MHz f
MAX
(external)
s
Low-power EE CMOS
s
10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
s
Varied product term distribution allows up to
16 product terms per output for complex
functions
s
Peripheral Component Interconnect (PCI)
compliant (-5/-7/-10)
s
Global asynchronous reset and synchronous
preset for initialization
s
Power-up reset for initialization and register
preload for testability
s
Extensive third-party software and programmer
support through FusionPLD partners
s
24-pin SKINNYDIP, 24-pin SOIC, 24-pin Flat-
pack and 28-pin PLCC and LCC packages save
space
s
5-ns and 7.5-ns versions utilize split lead-
frames for improved performance
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic
for replacing conventional SSI/MSI gates and flip-flops
at a reduced chip count.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, and active
high or active low. The output configuration is
determined by two bits controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PALCE22V10 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
BLOCK DIAGRAM
CLK/I
0
1
11
I
1
- I
11
Programmable
AND Array
(44 x 132)
8
10
12
14
16
16
14
12
10
8
RESET
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
PRESET
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
16564D-1
Publication#
16564
Rev.
D
Issue Date:
February 1996
Amendment
/0
2-217
AMD
CONNECTION DIAGRAMS
Top View
SKINNYDIP/SOIC/FLATPACK
I
2
I
1
CLK/I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
I
11
16564D-2
PLCC/LCC
CLK/I
0
V
CC
I/O
9
I/O
8
NC
1
4
I
3
I
4
I
5
NC
I
6
I
7
I
8
5
6
7
8
9
10
11
3
2
28 27 26
25
24
23
22
21
20
19
I/O
7
I/O
6
I/O
5
GND/NC*
I/O
4
I/O
3
I/O
2
12 13 14 15 16 17 18
I/O
0
I
10
GND
I/O
1
16564D-3
* For -5, this pin must be grounded for guaranteed data sheet performance. If not grounded, AC timing may degrade
by about 10%.
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK
I
I/O
NC
V
CC
= Clock
= Input
= Input/Output
= No Connect
= Supply Voltage
GND = Ground
2-218
PALCE22V10 Family
NC
I
11
I
9
AMD
ORDERING INFORMATION
Commercial and Industrial Products
AMD programmable logic products for commercial and industrial applications are available with several ordering options.
The order number (Valid Combination) is formed by a combination of:
PAL CE 22
V
10 H -5
P
C
/5
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V = Versatile
NUMBER OF OUTPUTS
POWER
Q = Quarter Power (55 mA I
CC
)
H = Half Power (90–140 mA I
CC
)
OPTIONAL PROCESSING
Blank = Standard Processing
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4
= First Revision
/5
= Second Revision
(Same Algorithm as /4)
OPERATING CONDITIONS
C = Commercial (0
°
C to +75
°
C)
I = Industrial (–40
°
C to +85
°
C)
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded
Chip Carrier (PL 028)
S = 24-Pin Plastic Gull-Wing
Small Outline Package
(SO 024)
SPEED
-5 = 5 ns t
PD
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-15 = 15 ns t
PD
-20 = 20 ns t
PD
-25 = 25 ns t
PD
Valid Combinations
JC
PALCE22V10-5
PC, JC
PALCE22V10H-7
/5
PALCE22V10H-10 PC, JC, SC, PI, JI, ZC
PALCE22V10Q-10
PC, JC
PALCE22V10H-15
PC, JC, PI, JI, ZC
Blank, /5, /4
PALCE22V10Q-15
PC, JC
/5
PALCE22V10H-20
PI, JI
/4
PC, JC, SC, PI, JI
PALCE22V10H-25
Blank, /4
PC, JC
PALCE22V10Q-25
Valid Combinations
Valid Combinations lists configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
PALCE22V10H-5/7/10/15/25, Q-10/15/25 (Com’l)
PALCE22V10H-10/15/20/25 (Ind)
2-219
AMD
FUNCTIONAL DESCRIPTION
The PALCE22V10 allows the systems engineer to im-
plement the design on-chip, by programming EE cells to
configure AND and OR gates within the device, accord-
ing to the desired logic function. Complex interconnec-
tions between gates, which previously required time-
consuming layout, are lifted from the PC board and
placed on silicon, where they can be easily modified dur-
ing prototyping or production.
Product terms with all connections opened assume the
logical HIGH state; product terms connected to both true
and complement of any single input assume the logical
LOW state.
The PALCE22V10 has 12 inputs and 10 I/O macrocells.
The macrocell (Figure 1) allows one of four potential out-
put configurations; registered output or combinatorial
I/O, active high or active low (see Figure 1). The con-
figuration choice is made according to the user’s design
specification and corresponding programming of the
configuration bits S0 – S1. Multiplexer controls are
connected to ground (0) through a programmable bit,
selecting the “0” path through the multiplexer. Erasing
the bit disconnects the control line from GND and it is
driven to a high level, selecting the “1” path.
The device is produced with a EE cell link at each input
to the AND gate array, and connections may be selec-
tively removed by applying appropriate voltages to the
circuit. Utilizing an easily-implemented programming al-
gorithm, these products can be rapidly programmed to
any customized pattern.
Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and
each macrocell output can be an I/O pin. Buffers for de-
vice inputs have complementary outputs to provide
user-programmable input signal polarity. Unused input
pins should be tied to V
CC
or GND.
AR
D Q
CLK
Q
SP
S
1
1
1
0
0
0
1
0
1
S
1
S
0
0
0
1
1
S
0
0
1
0
1
Output Configuration
Registered/Active Low
Registered/Active High
Combinatorial/Active Low
Combinatorial/Active High
I/O
n
0
1
0 = Programmed EE bit
1 = Erased (charged) EE bit
16564D-4
Figure 1. Output Logic Macrocell Diagram
2-220
PALCE22V10 Family
AMD
Registered Output Configuration
Each macrocell of the PALCE22V10 includes a D-type
flip-flop for data storage and synchronization. The flip-
flop is loaded on the LOW-to-HIGH transition of the
clock input. In the registered configuration (S
1
= 0), the
array feedback is from
Q
of the flip-flop.
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(S
1
= 1). In the combinatorial configuration the feedback
is from the pin.
AR
D
CLK
SP
Q
Q
S
0
= 0
S
1
= 0
S
0
= 0
S
1
= 1
Registered/Active Low
S
0
= 1
S
1
= 0
Q
Q
SP
Combinatorial/Active Low
S
0
= 1
S
1
= 1
AR
D
CLK
Registered/Active High
Combinatorial/Active High
16564D-5
Figure 2. Macrocell Configuration Options
PALCE22V10 Family
2-221
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