LTC4402-1/LTC4402-2
Multiband RF Power
Controllers for EDGE/TDMA
FEATURES
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DESCRIPTIO
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Supports AM Modulation in EDGE/TDMA (ANSI-136)
Applications
Single Output RF Power Amplifier Control
(LTC4402-1)
Dual Output RF Power Amplifier Control (LTC4402-2)
Internal Schottky Diode Detector with >40dB Range
Wide Input Frequency Range: 300MHz to 2.4GHz
Autozero Loop Cancels Offset Errors and
Temperature Dependent Offsets
Wide V
IN
Range: 2.7V to 6V
450kHz Loop Bandwidth
Allows Direct Connection to Battery
RF Output Power Set by External DAC
Internal Frequency Compensation
Rail-to-Rail Power Control Outputs
Low Operating Current: 1mA
Low Shutdown Current: < 10µA
PCTL Input Filter
Available in a 8-Pin MSOP Package (LTC4402-1)
and 10-Pin MSOP (LTC4402-2)
The LTC
®
4402-2 is a multiband RF power controller for
RF power amplifiers operating in the 300MHz to 2.4GHz
range. The LTC4402-2 has two outputs to control dual T
X
PA modules with two control inputs. An internal sample
and hold circuit enables the LTC4402-2 to be used with
AM modulation via the carrier or PA supply. The input
voltage range is optimized for operation from a single
lithium-ion cell or 3× NiMH.
RF power is controlled by driving the RF amplifier power
control pins and sensing the resultant RF output power.
The RF sense voltage is peak detected using an on-chip
Schottky diode. This detected voltage is compared to the
DAC voltage at the PCTL pin to control the output power.
The LTC4402-1 is a single output RF power controller
with identical performance to the LTC4402-2. The
LTC4402-1 has one output to control a single T
X
PA or
dual T
X
PA module with a single control input and is
available in an 8-pin MSOP package.
Internal and external offsets are cancelled over tempera-
ture by an autozero control loop. The shutdown feature
disables the part and reduces the supply current to
< 10µA.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
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Multiband GSM/GPRS/EDGE Cellular Phones
PCS Devices
Wireless Data Modems
U.S. TDMA Cellular Phones
TYPICAL APPLICATIO
LTC4402-2 Multiband EDGE Cellular Telephone Transmitter
LTC4402-2
1
Li-Ion
0.1µF
BSEL
V
HOLD
SHDN
DAC
9
8
7
6
V
IN
BSEL
V
HOLD
SHDN
PCTL
RF
V
PCA
V
PCB
GND
GND
10
2
3
4
5
850MHz/
900MHz
RF PA
50Ω
0.4pF
±
0.05pF
1.8GHz /
1.9GHz
RF PA
U
DIPLEXER
4402 TA01
U
U
4402f
1
LTC4402-1/LTC4402-2
ABSOLUTE
AXI U
RATI GS
V
IN
to GND ............................................... – 0.3V to 6.5V
V
PCA
, V
PCB
Voltage .................................. – 0.3V to 4.6V
PCTL Voltage ............................... – 0.3V to (V
IN
+ 0.3V)
RF Voltage ........................................ (V
IN
±
2.6V) to 7V
SHDN, V
HOLD
, BSEL Voltage
to GND ......................................... – 0.3V to (V
IN
+ 0.3V)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
V
IN
1
V
PCA
2
GND 3
GND 4
8
7
6
5
RF
V
HOLD
SHDN
PCTL
ORDER PART
NUMBER
LTC4402-1EMS8
MS8 PART MARKING
LTXF
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 160°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER
V
IN
Operating Voltage
I
VIN
Shutdown Current
I
VIN
Operating Current
V
PCA/B
V
OL
V
PCA/B
Dropout Voltage
V
PCA/B
Output Current
V
PCA/B
Enable Time
V
PCA/B
Bandwidth
V
PCA/B
Load Capacitance
V
PCA/B
Slew Rate
V
PCA/B
V
HOLD
Droop
V
HOLD
Time
V
PCA/B
Start Voltage
V
PCA/B
Voltage Clamp
SHDN, V
HOLD
, BSEL Input Threshold Low
SHDN = 0V
I
VPCA
= I
VPCB
= 0mA
CONDITIONS
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 3.6V, SHDN = V
IN
unless otherwise noted.
MIN
q
q
q
q
q
q
q
R
LOAD
= 400Ω, Enabled
I
LOAD
= 6mA, V
IN
= 2.7V
V
PCA/B
= 2.4V, V
IN
= 2.7V,
∆V
OUT
= 10mV
SHDN = High (Note 5)
C
LOAD
= 33pF, R
LOAD
= 400 (Note 7)
(Note 6)
V
PCTL
= 2V Step, C
LOAD
= 100pF, R
LOAD
= 400 (Note 3)
Unity Gain, V
PCTL
= 2V, V
HOLD
= High
Time from V
HOLD
High to Hold Switch Opening
Open Loop
PCTL = 1V, V
IN
= 5V
V
IN
= 2.7V to 6V
PCTL < 80mV
PCTL > 160mV
SHDN, V
HOLD
, BSEL Input Threshold High V
IN
= 2.7V to 6V
SHDN, BSEL, V
HOLD
Input Current
SHDN, BSEL, V
HOLD
= V
IN
= 3.6V
PCTL Input Voltage Range
PCTL Input Resistance
(Note 4)
2
U
U
W
W W
U
W
(Note 1)
I
VPCA/B ..................................................................................
10mA
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Maximum Junction Temperature ........................ 125°C
Lead Temperature (Soldering, 10 sec)................ 300°C
TOP VIEW
V
IN
V
PCA
V
PCB
GND
GND
1
2
3
4
5
10 RF
9 BSEL
8 V
HOLD
7 SHDN
6 PCTL
ORDER PART
NUMBER
LTC4402-2EMS
MS PART MARKING
LTXH
MS PACKAGE
10-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 160°C/W
TYP
10
1.5
MAX
6
20
2
0.1
V
IN
– 0.25
UNITS
V
µA
mA
V
V
mA
µs
kHz
kHz
2.7
0
6
9
450
260
11
q
100
2
1
100
pF
V/µs
µV/ms
ns
q
q
q
q
q
q
q
250
3.6
1.4
16
0
60
450
4
550
4.4
0.35
mV
V
V
V
µA
V
kΩ
4402f
24
90
36
2.4
120
LTC4402-1/LTC4402-2
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 3.6V, SHDN = V
IN
, unless otherwise noted.
PARAMETER
PCTL Input Filter
Autozero Range
RF Input Frequency Range
RF Input Power Range
Maximum DAC Zero-Scale Offset Voltage
that can be applied to PCTL
(Note 6)
F = 900MHz (Note 6)
F = 1800MHz (Note 6)
F = 2400MHz (Note 6)
Referenced to V
IN
q
q
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
TYP
270
MAX
400
UNITS
kHz
mV
MHz
dBm
dBm
dBm
300
–27 to 18
–25 to 18
–23 to 16
150
250
2400
RF Input Resistance
350
Ω
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Specifications are assured over the –40°C to 85°C temperature
range by design characterization and correlation with statistical process
controls.
Note 3:
Slew rate is measured open loop. The rise time at V
PCA
or V
PCB
is
measured between 1V and 2V.
Note 4:
Includes maximum DAC offset voltage and maximum control
voltage.
Note 5:
This is the time from SHDN rising edge 50% switch point to
V
PCA/B
= 250mV.
Note 6:
Guaranteed by design. This parameter is not production tested.
Note 7:
Bandwidth is calculated using the 10% to 90% rise time:
BW = 0.35/rise time
TYPICAL PERFOR A CE CHARACTERISTICS
PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV)
PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV)
10000
10000
PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV)
Detector Characteristics at 900MHz
1000
100
0.9GHz
AT 25°C
0.9GHz AT –30°C
10
0.9GHz AT 75°C
1
–26
–20 –14 –8
–2
4
10
RF INPUT POWER (dBm)
16
4402 G01
PI FU CTIO S
(LTC4402-1/LTC4402-2)
V
IN
(Pin 1):
Input Supply Voltage, 2.7V to 6V. V
IN
should
be bypassed with 0.1µF and 100pF ceramic capacitors.
V
PCA
(Pin 2):
Power Control Voltage Output. This pin
drives an external RF power amplifier power control pin.
The maximum load capacitance is 100pF. The output is
capable of rail-to-rail swings at low load currents. Selected
when BSEL is low.
U W
Detector Characteristics at 1800MHz
Detector Characteristics at 2400MHz
10000
1000
1.8GHz AT –30°C
100
1.8GHz
AT 25°C
1000
100
2.4GHz AT –30°C
2.4GHz AT 25°C
10
2.4GHz AT 75°C
1
–20
–14
–8
–2
4
RF INPUT POWER (dBm)
10
16
10
1.8GHz AT 75°C
1
–26 –20
–14 –8
–2
4
10
RF INPUT POWER (dBm)
16
4402 G02
4402 G03
U
U
U
V
PCB
(Pin 3): (LTC4402-2 Only)
Power Control Voltage
Output. This pin drives an external RF power amplifier
power control pin. The maximum load capacitance is
100pF. The output is capable of rail-to-rail swings at low
load currents. Selected when BSEL is high.
GND (Pin 3/4):
System Ground.
4402f
3
LTC4402-1/LTC4402-2
PI FU CTIO S
GND (Pin 4/5):
System Ground.
PCTL (Pin 5/6):
Analog Input. The external power control
DAC drives this input. The amplifier servos the RF power
until the RF detected signal equals the DAC signal applied
at this pin.
SHDN (Pin 6/7):
Shutdown Input. A logic low on the SHDN
pin places the part in shutdown mode. A logic high enables
the part after 10µs. SHDN has an internal 150k pull-down
resistor to ensure that the part is in shutdown when no input
is applied.
BLOCK DIAGRA
0.4pF
±0.05pF
50Ω
V
IN
250Ω
10
RF
V
IN
28pF
30k
60µA
4
5
GND
9µs
DELAY
60µA
150k
7
SHDN
4
W
U
U
U
(LTC4402-1/LTC4402-2)
V
HOLD
(Pin 7/8):
Asserted high prior to AM modulation,
opens control loop and holds voltage at V
PCA
or V
PCB
during
EDGE modulation.
BSEL (Pin 9): (LTC4402-2 Only)
Selects V
PCA
when low
and V
PCB
when high. This input has an internal 150k
resistor to ground.
RF (Pin 8/10):
Coupled RF Feedback Voltage . This input
is referenced to V
IN
. The frequency range is 300MHz to
2400MHz. This pin has an internal 250Ω termination, an
internal Schottky diode detector and peak detector
capacitor.
(LTC4402-2)
DIPLEXER
850MHz/900MHz
RF PA
RF PA
1.8GHz/1.9GHz
Li-Ion
1
TXENB
AUTOZERO
–
AZ
+
+
–
GAIN
COMPRESSION
–
GM
+
V
HOLD
+
–
30k
70mV
C
HOLD
270kHz
FILTER
38k
+
–
BUFFER
2
V
PCA
3
V
PCB
+
RFDET
–
22k
V
HOLD
12Ω
TXENB
V
REF
V
HOLD
150k
51k
150k
C
REF
MUX
CONTROL
PA
PB
100Ω
12Ω
100Ω
8
V
HOLD
6
PCTL
9
BSEL
4402 BD
4402f
LTC4402-1/LTC4402-2
APPLICATIONS INFORMATION
Operation
The LTC4402-1/-2 single/dual band RF power controller
integrates several functions to provide RF power control
over frequencies ranging from 300MHz to 2.4GHz. These
functions include an internally compensated amplifier to
control the RF output power, an autozero section to cancel
internal and external voltage offsets, an RF Schottky diode
peak detector and amplifier to convert the RF feedback
signal to DC, a multiplexer to switch the controller output
to either V
PCA
or V
PCB
, a V
PCA/B
overvoltage clamp, com-
pression and a bandgap reference.
Band Selection
The LTC4402-2 is designed for multiband operation. The
BSEL pin will select output V
PCA
when low and output
V
PCB
when high. For example, V
PCA
could be used to drive
an 850MHz/900MHz channel and V
PCB
a 1.8GHz/1.9GHz
channel. BSEL must be established before the part is
enabled. The LTC4402-1 can be used to drive a single RF
channel or dual channel with integral multiplexer.
Control Amplifier
The control amplifier supplies the power control voltage to
the RF power amplifier. A portion (typically – 19dB for low
frequencies and –14dB for high frequencies) of the RF
output voltage is coupled into the RF pin, to close the gain
control loop. When a DAC voltage is applied to PCTL, the
amplifier quickly servos V
PCA
or V
PCB
positive until the
detected feedback voltage applied to the RF pin matches
the voltage at PCTL. This feedback loop provides accurate
RF power control. V
PCA
or V
PCB
are capable of driving a
6mA load current and 100pF load capacitor.
RF Detector
The internal RF Schottky diode peak detector and ampli-
fier convert the coupled RF feedback voltage to a low
frequency voltage. This voltage is compared to the DAC
voltage at the PCTL pin by the control amplifier to close
the RF power control loop. The RF pin input resistance is
typically 250Ω and the frequency range of this pin is
300MHz to 2400MHz. The detector demonstrates excel-
lent efficiency and linearity over a wide range of input
power. The Schottky detector is biased at about 60µA and
drives an on-chip peak detector capacitor of 28pF.
Autozero
An autozero system is included to improve power pro-
gramming accuracy over temperature. This section can-
cels internal offsets associated with the Schottky diode
detector and control amplifier. External offsets associated
with the DAC driving the PCTL pin are also cancelled.
Offset drift due to temperature is cancelled between each
burst. The maximum offset allowed at the DAC output is
limited to 400mV. Autozeroing is performed after SHDN
is asserted high. An internal delay of typically 9µs enables
the V
PCA/B
output after the autozero has settled. When the
part is enabled, the autozero capacitors are held and the
V
PCA
or V
PCB
pin is connected to the buffer amplifier
output. The hold droop voltage of typically < 1µV/ms
provides for accurate offset cancellation.
Filter
There is a 270kHz filter included in the PCTL path. This
filter is trimmed at test.
Modes of Operation
Shutdown:
The part is in shutdown mode when SHDN is
low. V
PCA
and V
PCB
are held at ground and the power
supply current is typically 10µA.
Enable:
When SHDN is asserted high the part will auto-
matically calibrate out all offsets. This takes about 9µs and
is controlled by an internal delay circuit. After 9µs V
PCA
or
V
PCB
will step up to the starting voltage of 450mV. The
user can then apply the ramp signal. The user should wait
at least 11µs after SHDN has been asserted high before
applying the ramp. The DAC should be settled 2µs after
asserting SHDN high.
Hold:
When the V
HOLD
pin is low, the RF power control
feedback loop is closed and the LTC4402-X servos the
V
PCA
/V
PCB
pins according to the voltages at the PCTL and
RF inputs. When the V
HOLD
pin is asserted high, the RF
power control feedback loop is opened and the power
control voltage at V
PCA
or V
CPB
is held at its present level.
Generally, the V
HOLD
pin is asserted high after the power
up ramp has been completed and the desired RF output
power has been achieved. The power control voltage is
then held at a constant voltage during the EDGE modula-
tion time. After the EDGE modulation is completed and
prior to power ramping down, the V
HOLD
pin is set low.
4402f
U
W
U
U
5
FPGA/CPLD
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