IS26KS512S/256S/128S
IS26KL512S/256S/128S
512Mb/256Mb/128Mb
HyperFlash™ Family Non-Volatile Memory
DATA SHEET
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A3
08/10/2017
1
IS26KS128S/256S/512S
IS26KL128S/256S/512S
HyperFlash Family Non-Volatile
Memory
IS26KS512S
/
IS26KL512S
512 Mbit (64 Mbyte)
IS26KS256S
/
IS26KL256S
256 Mbit (32 Mbyte)
IS26KS128S
/
IS26KL128S
128 Mbit (16 Mbyte)
CMOS 1.8 Volt
or
3.0 Volt Core and I/O
™
AUGUST
2017
Features
3.0V I/O, 11 bus signals
– Single ended clock
1.8V I/O, 12 bus signals
– Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
– HyperFlash™ memories use RWDS only as a Read Data
Strobe
Up to 333 MB/s sustained read throughput
Double-Data Rate (DDR) – two data transfers per clock
166-MHz clock rate (333 MB/s) at 1.8V V
CC
100-MHz clock rate (200 MB/s) at 3.0V V
CC
96-ns initial random read access time
– Initial random access read latency: 5 to 16 clock cycles
Sequential burst transactions
Configurable Burst Characteristics
– Wrapped burst lengths:
– 16 bytes (8 clocks)
– 32 bytes (16 clocks)
– 64 bytes (32 clocks)
– Linear burst
– Hybrid option — one wrapped burst followed by linear burst
– Wrapped or linear burst type selected in each transaction
– Configurable output drive strength
Low Power Modes
– Active Clock Stop During Read: 12 mA, no wake-up
required
– Standby: 25 µA (typical), no wake-up required
– Deep Power-Down: 8 µA (typical)
– 300 µs wake-up required
INT# output to generate external interrupt
– Busy to Ready Transition
– ECC detection
RSTO# output to generate system level power-on reset
– User configurable RSTO# Low period
512-byte Program Buffer
Sector Erase
– Uniform 256-kB sectors
– Optional Eight 4-kB Parameter Sectors (32 kB total)
Advanced Sector Protection
– Volatile and non-volatile protection methods for each
sector
Separate 1024-byte one-time program array
Operating Temperature
– Industrial (–40°C to +85°C)
–
Extended
(–40°C to +105°C)
– Extended
+
(–40°C to +125°C)
– Automotive, AEC-Q100 Grade
A1
(–40°C to +85°C)
– Automotive, AEC-Q100 Grade
A2
(–40°C to +105°C)
– Automotive, AEC-Q100 Grade
A3
(–40°C to +125°C)
ISO/TS16949 and AEC Q100 Certified
Endurance
– 100,000 program/erase cycles
Retention
– 20 year data retention
Erase and Program Current
– Max Peak
100 mA
Packaging Options
– 24-Ball FBGA
Additional Features
– ECC 1-bit correction, 2-bit detection
– CRC (Check-value Calculation)
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A3
08/10/2017
2
IS26KS128S/256S/512S
IS26KL128S/256S/512S
Performance Summary
Read Access Timings
Maximum Clock Rate at 1.8V V
CC
/V
CC
Q
Maximum Clock Rate at 3.0V V
CC
/V
CC
Q
Maximum Access Time, (t
ACC
)
Maximum CS# Access Time to First Word @ 166 MHz
Typical Program / Erase Times
Single Word Programming (2B = 16b)
Write Buffer Programming (512B = 4096b)
Sector Erase Time (256 kB = 2 Mb)
Typical Current Consumption
Burst Read (Continuous Read at 166 MHz)
Power-On Reset
Sector Erase Current
Write Buffer Programming Current
Standby (CS# = High)
Deep Power-Down (CS# = High, 85°C)
80 mA
80 mA
60 mA
60 mA
25 µA
30 µA (512 Mb)
4 µA (all other densities)
500 µs (~4 kB/s)
475 µs (~1 MB/s)
930 ms (~282 kB/s)
166 MHz
100 MHz
96 ns
118 ns
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A3
08/10/2017
3
IS26KS128S/256S/512S
IS26KL128S/256S/512S
Contents
1.
1.1
1.2
2.
2.1
3.
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
6.
6.1
6.2
6.3
7.
7.1
7.2
General Description....................................................
4
DDR Center Aligned Read Strobe Functionality
(DCARS).......................................................................
7
Error Detection and Correction Functionality................
7
Connection Diagram...................................................10
FBGA 24-Ball 5 x 5 Array Footprint..............................10
Signal Description
.................................................... 11
HyperBus Protocol
...................................................
Command / Address Bit Assignments........................
Read Operations ........................................................
HyperFlash Read with DCARS Timing.......................
Write Operations ........................................................
12
12
13
16
17
9.1
9.2
10.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Endurance ...................................................................
70
Data Retention ............................................................
70
Electrical Specifications............................................
71
Absolute Maximum Ratings......................................... 71
Thermal Impedance .................................................... 72
Latchup Characteristics............................................... 72
Operating Ranges ....................................................... 72
DC Characteristics (CMOS Compatible) ..................... 73
Power-Up and Power-Down........................................ 75
Power-Off with Hardware Data Protection .................. 79
Power Conservation Modes ........................................ 79
Hardware Interface
Address Space Maps................................................
19
Flash Memory Array ...................................................
20
Device ID and CFI (ID-CFI) ASO................................ 22
Embedded Operations..............................................
Embedded Algorithm Controller (EAC).......................
Program and Erase Summary....................................
Data Protection...........................................................
24
24
25
49
11. Timing Specifications................................................
81
11.1 AC Test Conditions ..................................................... 81
11.2 AC Characteristics....................................................... 82
12.
13.
14.
15.
Embedded Algorithm Performance..........................
87
Ordering
Rule
................................................. 88
Ordering Information
.................................................
89
Package Drawing
........................................................ 91
Device ID and Common Flash Interface
(ID-CFI) ASO Map
....................................................... 59
Device ID and Common Flash Interface
(ID-CFI) ASO Map — Standard .................................. 59
Device ID and Common Flash Interface
(ID-CFI) ASO Map — Automotive Grade
/ AEC-Q100 ................................................................ 64
Software Interface Reference
.................................. 65
Command Summary................................................... 65
Data Integrity.............................................................
70
8.
8.1
9.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A3
08/10/2017
4
IS26KS128S/256S/512S
IS26KL128S/256S/512S
1.
General Description
The ISSI HyperFlash family of products are high-speed CMOS, MirrorBit
NOR flash devices with the HyperBus low signal
count DDR (Double Data Rate) interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per
clock cycle on the data (DQ) signals. A read or write access for the HyperFlash consists of a series of 16-bit wide, one clock cycle
data transfers at the internal HyperFlash core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ
signals.
Both data and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock input signals are
used for signal capture by the HyperFlash device when receiving command/address/data information on the DQ signals. The Read
Data Strobe (RWDS) is an output from the HyperFlash device that indicates when data is being transferred from the memory to the
host. RWDS is referenced to the rising and falling edges of CK during the data transfer portion of read operations.
Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned with the
transitions of RWDS.
Read and write operations to the HyperFlash device are burst oriented. Read transactions can be specified to use either a wrapped
or linear burst. During wrapped operation, accesses start at a selected location and continue for a configured number of locations in
a group wrap sequence. During linear operation accesses start at a selected location and continue in a sequential manner until the
read operation is terminated, when CS# returns High. Write transactions transfer one or more16-bit values.
Figure 1. Logic Block Diagram
Mandatory Signals
CS#
CK
CK#
DQ[7:0]
RWDS
Optional Signals
C
O
M
M
A
N
D
D
E
C
O
D
E
R
CONTROL
LOGIC
X
ADDR
RESET#
RSTO#
INT#
PSC
PSC#
X
X
X
X
D
D
D E
D E
E
E CC
C D
CD
D
D EE
E
E RR
R S
R S
S
S
MEMORY ARRAY
SENSE AMPLIFIER
ADDRESS
REGISTER
RWDS
GENERATOR
Y
ADDR
Y DECODERS
Data Latch
The HyperFlash family consists of multiple densities, 1.8V/3.0V core and I/O, non-volatile, synchronous flash memory devices.
These devices have an 8-bit (1-byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read operations
provide 16 bits of data during each clock cycle (8 bits on each clock edge). Write operations take 16 bits of data from each clock
cycle (8 bits on each clock edge).
Each random read accesses a 32-byte length and aligned set of data called a page. Each page consists of a pair of 16-byte aligned
groups of array data called half-pages. Half-pages are aligned on 16-byte address boundaries. A read access requires two clock
cycles to define the target half-page address and the burst type, then an additional initial latency. During the initial latency period the
third clock cycle will specify the starting address within the target half-page. After the initial data value has been output, additional
data can be read from the Page on subsequent clock cycles in either a wrapped or linear manner. When configured in linear burst
mode, while a page is being burst out, the device will automatically fetch the next sequential page from the MirrorBit flash memory
array. This simultaneous burst output while fetching from the array allows for a linear sequential burst operation that can provide a
sustained output of 333 MB/s data rate (1-byte (8-bit data bus) * 2 (Data on both clock edges) * 166 MHz = 333 MB/s).
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A3
08/10/2017
5
NXP MCU
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