MR16R162C(G)MN0
MR18R162C(G)MN0
Change History
Version 0.9 (January 2000)
- Preliminary
* First copy.
* Based on the 1.02ver 128/144Mbit RDRAMs base RIMM Datasheet
Version 1.0 (October 2000)
- Preliminary
* Based on the 1.0ver Rambus 256/288Mb RDRAMs base RIMM datasheet
Page No.
Change Description
1
6
7
8
9
- Add the x16 RDRAM product (*Note, x16 is same die as x18)
- Correct V
CMOS
to V
DD
& Add V
SPD
condition
- Add the current values for RIMM Module
- Relax the RIMM CMOS delta tPD spec. from
±100ps
to
±250ps
- Add delta tPD spec for SCK-CMD of
±200ps
- Relax tPD as follows
16d
OLD
(-800 & -711MHz/-600MHz)
8d
1.50 / 1.60ns
1.56ns
4d
1.25ns
1.28ns
2.06 / 2.10ns
2.11ns
NEW
(-800,-711&-600MHz)
- Correct 600MHz RIMM attenuation spec
16d
OLD
NEW
21%
18.5%
12d
18%
15.5%
8d
10%
12.5%
6d
9%
11.5%
4d
8%
10.5%
10
11
12
- Revise the PCB height from 1250mil interrim solution to "1,375"mil
- Revise the "Physical Dimension-2" for heat spreader
- Correct T-point from 0.15±0.10mm to 0.30±0.10mm
Version 1.0a (November 2000)
7
-Change I
DD1
and I
DD4
parameters
Version 1.1 (March 2000)
-Only 12/16d RIMM are using 8layer PCB.
The specifications of 4/6/8d RIMM were seperated from that of 12/16d
Page 0
Version 1.1 Mar. 2001
MR16R162C(G)MN0
MR18R162C(G)MN0
(16Mx16)*12(16)pcs RIMM
TM
Module based on 256Mb M-die, 32s banks,16K/32ms Ref, 2.5V
(16Mx18)*12(16)pcs RIMM
TM
Module based on 288Mb M-die, 32s banks,16K/32ms Ref, 2.5V
Overview
The Rambus
®
RIMM™ module is a general purpose high-
performance memory module suitable for use in a broad
range of applications including computer memory, personal
computers, workstations, and other applications where high
bandwidth and low latency are required.
The Rambus RIMM module consists of 256Mb/288Mb
Direct Rambus DRAM devices. These are extremely high-
speed CMOS DRAMs organized as 16M words by 16 or 18
bits. The use of Rambus Signaling Level (RSL) technology
permits 600 MHz, 711 MHz or 800 MHz transfer rates while
using conventional system and board design technologies.
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per 16 bytes).
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed,
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM's 32-bank architecture supports
up to four simultaneous transactions per device.
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins
available for RIMM modules.
Table 1: Part Number by Freq. & Latency
Speed
Organiza-
tion
I/O Freq.
(MHz)
800
711
600
800
711
600
t
RAC
(Row
Access
Time) ns
45
45
53.3
45
45
53.3
Part Number
Bin
192M x 16/18 -CK8
-CK7
-CG6
256M x 16/18 -CK8
-CK7
-CG6
MR16/18R162CMN0-CK8
MR16/18R162CMN0-CK7
MR16/18R162CMN0-CG6
MR16/18R162GMN0-CK8
MR16/18R162GMN0-CK7
MR16/18R162GMN0-CG6
Form Factor
The Rambus RIMM modules are offered in 184-pad 1mm
edge connector pad pitch suitable for 184 contact RIMM
connectors. Figure 1 below, shows a sixteen device Rambus
RIMM module.
Features
♦
High speed 800, 711 and 600MHz RDRAM storage
♦
184 edge connector pads with 1mm pad spacing
♦
Module PCB size : 133.35mm x 34.93mm x 1.27mm
(5.25” x 1.375” x 0.05”)
♦
Each RDRAM has 32 banks, for a total of 512, 384 banks
on each 512/576MB, 384/432MB module respectively
♦
Gold plated edge connector pad contacts
♦
Serial Presence Detect(SPD) support
♦
Operates from a 2.5 volt supply (±5%)
♦
Powerdown self refresh modes
♦
Separate Row and Column buses for higher efficiency
♦
uBGA package (92 balls)
Note: On double sided modules, RDRAMs are also installed on bottom side of PCB.
Figure 1: Rambus RIMM Module shown with heat spreader removed
Page 1
Version 1.1 Mar. 2001
MR16R162C(G)MN0
MR18R162C(G)MN0
Table 2: Module Pad Numbers and Signal Names
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
Pin Name
Gnd
LDQA8
Gnd
LDQA6
Gnd
LDQA4
Gnd
LDQA2
Gnd
LDQA0
Gnd
LCTMN
Gnd
LCTM
Gnd
NC
Gnd
LROW1
Gnd
LCOL4
Gnd
LCOL2
Gnd
LCOL0
Gnd
LDQB1
Gnd
LDQB3
Gnd
LDQB5
Gnd
LDQB7
Gnd
LSCK
Vcmos
SOUT
Vcmos
NC
Gnd
NC
Vdd
Vdd
NC
NC
NC
NC
Pin
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
Pin Name
Gnd
LDQA7
Gnd
LDQA5
Gnd
LDQA3
Gnd
LDQA1
Gnd
LCFM
Gnd
LCFMN
Gnd
NC
Gnd
LROW2
Gnd
LROW0
Gnd
LCOL3
Gnd
LCOL1
Gnd
LDQB0
Gnd
LDQB2
Gnd
LDQB4
Gnd
LDQB6
Gnd
LDQB8
Gnd
LCMD
Vcmos
SIN
Vcmos
NC
Gnd
NC
Vdd
Vdd
NC
NC
NC
NC
Pin
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
Pin Name
NC
NC
NC
NC
Vref
Gnd
SCL
Vdd
SDA
SVdd
SWP
Vdd
RSCK
Gnd
RDQB7
Gnd
RDQB5
Gnd
RDQB3
Gnd
RDQB1
Gnd
RCOL0
Gnd
RCOL2
Gnd
RCOL4
Gnd
RROW1
Gnd
NC
Gnd
RCTM
Gnd
RCTMN
Gnd
RDQA0
Gnd
RDQA2
Gnd
RDQA4
Gnd
RDQA6
Gnd
RDQA8
Gnd
Pin
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
Pin Name
NC
NC
NC
NC
Vref
Gnd
SA0
Vdd
SA1
SVdd
SA2
Vdd
RCMD
Gnd
RDQB8
Gnd
RDQB6
Gnd
RDQB4
Gnd
RDQB2
Gnd
RDQB0
Gnd
RCOL1
Gnd
RCOL3
Gnd
RROW0
Gnd
RROW2
Gnd
NC
Gnd
RCFMN
Gnd
RCFM
Gnd
RDQA1
Gnd
RDQA3
Gnd
RDQA5
Gnd
RDQA7
Gnd
Page 2
Version 1.1 Mar. 2001
MR16R162C(G)MN0
MR18R162C(G)MN0
Table 3: Module Connector Pad Description
Signal
Gnd
Pins
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
B10
B12
I
RSL
I/O
Type
Description
Ground reference for RDRAM core and interface. 72 PCB
connector pads.
LCFM
LCFMN
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
Serial Command used to read from and write to the control
registers. Also used for power management.
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. LDQA8 is non-func-
tional on modules with x16 RDRAM devices
Data bus B. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. LDQB8 is non-func-
tional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information
for row accesses.
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
These pads are not connected. These 24 connector pads are
reserved for future use.
I
I
RSL
V
CMOS
RSL
RSL
LCMD
LCOL4..
LCOL0
LCTM
LCTMN
B34
A20, B20, A22, B22, A24
I
I
A14
A12
I
RSL
LDQA8..
LDQA0
A2, B2, A4, B4, A6, B6, A8, B8, A10
I/O
RSL
LDQB8..
LDQB0
LROW2..
LROW0
LSCK
NC
B32, A32, B30, A30, B28, A28, B26,
A26, B24
B16, A18, B18
I/O
RSL
I
I
RSL
V
CMOS
A34
A16, B14, A38, B38, A40, B40, A43,
B43, A44, B44, A45, B45, A46, B46,
A47, B47, A48, B48, A49, B49, A50,
B50, A77, B79
B83
RCFM
I
I
RSL
RSL
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
Serial Command Input. Pin used to read from and write to the
control registers. Also used for power management.
RCFMN
RCMD
B81
B59
I
V
CMOS
Page 3
Version 1.1 Mar. 2001
MR16R162C(G)MN0
MR18R162C(G)MN0
Signal
RCOL4..
RCOL0
RCTM
Pins
A73, B73, A71, B71, A69
A79
I/O
I
Type
RSL
Description
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. RDQA8 is non-func-
tional on modules x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. RDQB8 is non-func-
tional on modules x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information
for row accesses.
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
Serial Presence Detect Data (Open Collector I/O).
Serial I/O for reading from and writing to the control registers.
Attaches to SIO0 of the first RDRAM on the module.
Serial I/O for reading from and writing to the control registers.
Attaches to SIO1 of the last RDRAM on the module.
SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1
and SA2.
I
SV
DD
Serial Presence Detect Write Protect (active high). When low,
the SPD can be written as well as read.
CMOS I/O Voltage. Used for signals CMD, SCK, SIN,
SOUT.
Supply voltage for the RDRAM core and interface logic.
Logic threshold reference voltage for RSL signals.
I
I
RSL
RSL
RCTMN
RDQA8..
RDQA0
A81
A91, B91, A89, B89, A87, B87, A85,
B85, A83
I/O
RSL
RDQB8..
RDQB0
B61, A61, B63, A63, B65, A65, B67,
A67, B69
I/O
RSL
RROW2..
RROW0
RSCK
B77, A75, B75
A59
I
RSL
I
I
I
I
I
I/O
I/O
I/O
V
CMOS
SV
DD
SV
DD
SV
DD
SV
DD
SV
DD
V
CMOS
V
CMOS
SA0
SA1
SA2
SCL
SDA
SIN
B53
B55
B57
A53
A55
B36
SOUT
SV
DD
SWP
V
CMOS
Vdd
Vref
A36
A56, B56
A57
A35, B35, A37, B37
A41, A42, A54, A58, B41, B42, B54,
B58
A51, B51
Page 4
Version 1.1 Mar. 2001
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
