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ispPAC 20
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
In-System Programmable Analog Circuit
Features
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG
— Two Instrument Amplifier Gain/Attenuation Stages
— Signal Summation (Up to 3 Inputs)
— Precision Active Filtering (10kHz to 100kHz)
— 8-Bit DAC and Fast Dual Comparator
— Non-Volatile E
2
CMOS
®
Cells (10,000 Cycles)
— IEEE 1149.1 JTAG Serial Port Programming
• LINEAR ELEMENT BUILDING BLOCKS
— Programmable Gain Range (0dB to 40dB)
— Bandwidth of 550kHz (G=1), 330kHz (G=10)
— Low Distortion (THD < -74dB max @ 10kHz)
— Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL I/O
— High CMR (69dB) Instrument Amplifier Inputs
— 2.5V Common Mode Reference on Chip
— Rail-to-Rail Voltage Outputs
— Single Supply 5V Operation
• 44-PIN PLASTIC PLCC AND TQFP PACKAGES
• APPLICATIONS INCLUDE INTEGRATED:
— Single +5V Supply Signal Conditioning
— Active Filters, Gain Stages, Summing Blocks
— Analog Front Ends, 12-Bit Data Acq. Systems
— Precision Voltage Controlled Oscillator
— Synchronous Detection Circuits
— Precision Rectification & Other Non-Linear Functions
®
Functional Block Diagram
VCC
MSEL
GND
OUT1
OUT2
IN1
IA
IA
OA
CP
Logic
CP1OUT
Logic
Window
IN2
CP
IA
IN3
IA
OA
3VREF
1.5VREF
CP2OUT
Analog Routing Pool
CPIN
E
2
CMOS Mem
Auto-Cal
Reference
ISP Control
DAC
DACOUT
Description
The ispPAC20 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E
2
CMOS technology.
Analog building blocks, called PACblocks, replace tradi-
tional analog components such as opamps and active
filters, eliminating the need for most external resistors and
capacitors. Also included are an 8-bit DAC and dual com-
parators. With no requirement for external configuration
components, ispPAC20 expedites the design process,
simplifying prototype circuit implementation and change,
while providing high-performance integrated functionality.
Designers configure the ispPAC20 and verify its perfor-
mance using PAC-Designer
®
, an easy-to-use, Microsoft
Windows
®
compatible program. Device programming is
supported using PC parallel port I/O operations.
The ispPAC20 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-System
Programming capability enables programming, verification
and reconfiguration if desired, directly on the printed circuit
board.
Typical Application Diagram
5V
Vin
5V
12-Bit
Differential
Input ADC
Copyright © 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
PC
VREFOUT
ENSPI
D0...D7
DMODE
CAL
JTAG/SPI
ispPAC20
CS
CMVIN
Ain+
Ain-
Ref+
DAC
Ref-
May 2001
pac20_05
1
Specifications
ispPAC20
T
A
= 25
°
C; V
S
= 5.0V; Signal path = V
IN
to V
OUT
of one PACblock (second input unused); 1V
≤
V
OUT
≤
4V; Gain = 1; Output load
= 200pf, 1MΩ. Feedback enabled; Feedback capacitor = minimum; Auto-cal initiated immediately prior. (Unless otherwise specified).
Ω
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
DC Electrical Characteristics
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX. UNITS
PACblock Analog Input
V
IN±
(1)
Input Voltage Range
V
IN-DIFF
Differential Input Voltage Swing (2)
V
OS
(2)
Differential Offset Voltage (Input Referred)
∆V
OS
/∆T
R
IN
C
IN
I
B
e
N
Differential Offset Voltage Drift
Input Resistance
Input Capacitance
Input Bias Current
Input Noise Voltage Density
Applied to Either V
IN+
or V
IN–
2| V
IN+
– V
IN–
|
G = 10
G=1
-40 to +85°C
1
6
20
0.2
50
10
9
2
3
38
0.1
9.6
10
2.475
0
4
100
1.0
at DC
At 10kHz, Referred to Input, G = 10
Present at Either V
OUT+
or V
OUT–
2| V
OUT+
– V
OUT–
|
Source/Sink
(V
OUT+
+ V
OUT-
)/2 ; V
IN+
= V
IN–
Each individual PACblock
R
L
= 300Ω Differential
Between Two Inputs of Same PACblock
-40 to +85°C
Differential at 1kHz
Single-ended at 1kHz
V
V
p-p
µV
mV
µV/°C
Ω
pF
pA
nV/√Hz
V
V
p-p
mA
V
dB
%
%
ppm/°C
dB
dB
PACblock Analog Output
V
OUT±
Output Voltage Range
V
OUT-DIFF
Differential Output Voltage Swing (2)
I
OUT±
Output Current
V
CM
Common Mode Output Voltage
PACblock Static Performance
G
Programmable Gain Range
Gain Error
∆G/∆T
PSR
Gain Matching
Gain Drift
Power Supply Rejection
4.9
2.500
2.525
26
4.0
3.0
20
80
77
-0.2
1.25
50
50
350
40
80
8
+0.2
3.25
Common Mode Reference Output (VREF
OUT
)
VREF
OUT
Output Voltage Range
CMV
IN
(4)
IREF
OUT
Common Mode Output Voltage Input
Output Voltage Drift
Output Current
Nominally 2.500V
Optional External VREF
OUT
Reference Voltage
-40 to +85°C
Source
Sink
10MHz Bandwidth; 1µF Bypass Capacitor
1kHz
%
V
ppm/°C
µA
µA
µV
RMS
dB
bits
lsb
lsb
%
ppm/°C
mV
V
dB
µV/°C
V
V
mA
V/µs
µs
°C
°C
Output Noise Voltage
Power Supply Rejection
Digital-to-Analog Converter (DAC) PACell
INL
DNL
∆/∆T
V
OS
V
CM
PSR
∆V
OS
/∆T
FSR
V
OUT±
I
OUT±
Resolution
Integral Non-Linearity Error
Differential Non-Linearity
Gain Error
Gain Drift
Differential Offset Voltage
Common Mode Output Voltage
Power Supply Rejection
Differential Offset Voltage Drift
Differential Full Scale Range
Voltage Output Range
Output Current
0.1%
Guaranteed Monotonic
-40 to +85°C
(D
OUT+
+ D
OUT-
)/2
Differential at 1kHz
-40 to +85°C
DAC Code 00h to FFh
R
L
= 1KΩ Differential
Source/Sink
6V
DIFF
Input Step
-40
-65
2.495
20
±0.5
±1.0
2.5
2
2.500
80
50
6.0
1
10
1.3
4.8
4
2.505
SR
Output Slew Rate
t
S
Output Settling Time
Temperature Range
Operation
Storage
6.0
+85
+150
2
Specifications
ispPAC20
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
DC Electrical Characteristics (Continued)
SYMBOL
Comparator PACells
A
V
V
OS
∆V
OS
/∆T
PSR
t
P
Voltage Gain
Input Offset Voltage
Differential Offset Voltage Drift
Power Supply Rejection
Programmable Hysteresis
Propagation Delay
Input Common Mode Input Range
Input Common Mode Rejection Ratio
Erase Program Cycles
Digital I/O
V
IL
V
IH
I
IL
, I
IH
V
OL
(5)
V
OH
(5)
Power Supplies
V
S
I
S
P
D
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
Output High Voltage
Operating Supply Voltage
Supply Current
Power Dissipation
V
S
= 5.0V
V
S
= 5.0V
108
5
50
80
±47
750
150
0
60
10K
0
2.0
0V
≤
TCK Input
≤
V
S
0V
≤
All Other Inputs
≤
V
S
I
OL
= 4.0mA
I
OH
= -1.0mA
0.8
V
S
±10
+40/-70
0.5
5.0
dB
mV
µV/°C
dB
mV
ns
ns
V
dB
cycles
V
V
µA
µA
V
V
V
mA
mW
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNITS
-40 to +85°C
Differential at 1kHz
On or Off
Overdrive = 10mV
Overdrive = 100mV
CMRR
Programming
2.4
4.75
5.0
5.25
21
105
AC Electrical Characteristics
SYMBOL
PARAMETER
Differential
Single-Ended
Differential
Single-Ended
SNR
CMR
BW
BW
FP
SR
t
S
Signal to Noise
G = 1 to 10
Common Mode Rejection (V
IN
= 1V to 4V)
Note: V
IN+
and V
IN-
connected together
Small Signal Bandwidth
G=1
G = 10
Full Power Bandwidth
Slew Rate
0.1%
V
IN
= 6V
DIFF
, V
OUT
= -3dB, G=1
5.0
6V
DIFF
Input Step
Between Any Two Channels
Number of Poles in Range > 120
Deviation From Calculated Value
10kHz to 100kHz
-40 to +85°C
10
1.0
0.02
CONDITION
F
IN
= 10kHz
F
IN
= 100kHz
0.1Hz to 100kHz
10kHz
100kHz
MIN.
TYP.
-88
-72
-67
-63
103
69
55
550
330
330
7.5
2.0
-90
MAX.
-74
-62
UNITS
dB
dB
dB
dB
dB
dB
dB
kHz
kHz
kHz
V/µs
µs
dB
PACblock Dynamic Performance
THD
Total Harmonic Distortion
Settling Time
Crosstalk
PACell Filter Characteristics
F
0
∆F
0
DF
0
/DT
Filter Pole Programming Range
Absolute Pole Frequency Accuracy
Pole Step Size (Between Calculated Poles)
Pole Frequency Change vs. Temperature
100
5.0
3.2
kHz
%
%
%/°C
Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also subject
to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) Refer to theory of operation section later in this datasheet
for explanation of differential voltage swing computation. (3) To insure full spec performance an additional auto-calibration should be performed
after initial turn-on and the device reaches thermal stability.(4) The user-provided voltage on this pin (CMV
IN
) becomes an optional (selected via
programming) alternative to the default 2.5V VREF
OUT
. (5) Includes TDO, CP1OUT, CP2OUT and WINDOW output logic pins.
3
Specifications
ispPAC20
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Absolute Maximum Ratings
Supply Voltage V
S
....................................... -0.5 to +7V
Logic and Analog Input Voltage Applied ........... 0 to V
S
Logic and Analog Output Short Circuit Duration ..... Indefinite
Lead Temperature (Soldering, 10 sec.) .............. 260°C
Ambient Temperature with Power Applied ... -55 to 125°C
Storage Temperature ................................ -65 to 150°C
Note: Stresses above those listed may cause permanent
damage to the device. These are stress only ratings and
functional operation of the device at these or at any other
conditions above those indicated in the operational sec-
tions of this specification is not implied.
Package Options
ispPAC20
ispPAC20
44-Pin PLCC
44-Pin TQFP
Part Number Description
ispPAC 20 – XX X X
Device Family
Device Number
Performance Grade
01 = Standard
Package
J = PLCC
T = TQFP
Grade
I = Industrial Temperature
ispPAC20 Ordering Information
Ordering Number
ispPAC20-01JI
ispPAC20-01TI
Package
44-Pin PLCC
44-Pin TQFP
DACOUT+
DACOUT–
DACOUT–
VREFOUT
DACOUT+
VREF
OUT
ENSPI
CMVin
ENSPI
CMVin
MSEL
TEST
MSEL
TEST
GND
CAL
IN3–
GND
CAL
IN3–
VS
6
IN3+
IN1–
IN1+
OUT1–
OUT1+
GND
OUT2+
OUT2–
IN2+
IN2–
VS
7
8
9
10
11
12
13
14
15
16
17
IA
IA
IA
5
4
3
2
1 44 43 42 41 40
39
OA
CP
44 43 42 41 40 39 38 37 36 35 34
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
CPIN+
CPIN–
GND
VS
33
IN3+
IN1–
IN1+
OUT1–
OUT1+
GND
OUT2+
OUT2–
IN2+
IN2–
VS
1
2
3
4
5
6
7
8
9
10
11
38
37
36
35
34
33
32
31
IA
OA
CP
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
CPIN+
CPIN–
GND
32
31
30
29
IA
IA
IA
OA
CP
OA
CP
28
27
26
25
IA
Analog Routing Pool
Analog Routing Pool
E2CMOS Mem
Auto-Cal
Reference
DAC
ISP Control
E2CMOS Mem
Auto-Cal
Reference
DAC
ISP Control
30
29
24
23
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
TDI
TMS
TCK
PC
CS
TDO
DMODE
VS
WINDOW
CP1OUT
CP2OUT
TDI
TMS
TCK
Pin Diagram
44 PLCC Package
PC
CS
TDO
DMODE
VS
WINDOW
CP1OUT
CP2OUT
Pin Diagram
44 TQFP Package
4
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