Datasheet
ISL89163, ISL89164, ISL89165
High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs
The
ISL89163, ISL89164,
and
ISL89165
are
high-speed, 6A, dual channel MOSFET drivers with
enable inputs.
Precision thresholds on all logic inputs allow the use
of external RC circuits to generate accurate and
stable time delays on both the main channel inputs,
INA and INB, and the enable inputs, ENA and ENB.
The precision delays capable of these precise logic
thresholds make these parts valuable for dead time
control and synchronous rectifiers. Note, the enable
and input logic inputs can be interchanged for
alternate logic implementations.
Three input logic thresholds are available:
• 3.3V (CMOS)
• 5.0V (CMOS or TTL compatible)
• CMOS thresholds that are proportional to V
DD
At high switching frequencies, these MOSFET drivers
use a minimal amount of internal bias currents.
Separate, non-overlapping drive circuits are used to
drive each CMOS output FET to prevent
shoot-through currents in the output stage.
The start-up sequence is designed to prevent
unexpected glitches when V
DD
is being turned on or
turned off. When V
DD
< ~1V, an internal 10kΩ resistor
between the output and ground helps to keep the
output voltage low. When ~1V < V
DD
< UV, both
outputs are driven low with significantly low resistance
as the logic inputs are ignored, which ensures that the
driven FETs are off. When V
DD
> UVLO, and after a
short delay, the outputs begin to respond to the logic
inputs.
Features
• Dual output, 6A peak currents, can be paralleled
• Dual AND-ed input logic, (input and enable)
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
• Very low thermal impedance (θ
JC
= 3°C/W)
• Hysteretic Input logic levels for 3.3V CMOS, 5V
CMOS, TTL, and Logic levels proportional to V
DD
• Precision threshold inputs for time delays with
external RC components
• 20ns rise and fall time driving a 10nF load.
Applications
• Synchronous Rectifier (SR) driver
• Switch mode power supplies
• Motor drives, Class D amplifiers, UPS, inverters
• Pulse transformer driver
• Clock/line driver
Related Literature
For a full list of related documents, visit our website:
•
ISL89163, ISL89164, ISL89165
device pages
3.0
Option B Thresholds (5.0V)
Positive Threshold Limits
2.5
2.0
1.5
1.0
0.5
0.0
-40 -25 -10
Negative Threshold Limits
V
DD
ENB
ENA
INA
GND
INB
1
2
3
4
EPAD
8
7
6
5
OUTB
4.7µF
OUTA
5
20 35 50 65 80
Temperature (°C)
95 110 125
Figure 1. Typical Application
Figure 2. Temperature Stable Logic Thresholds
FN7707 Rev.6.00
Jul.9.19
Page 1 of 22
ISL89163, ISL89164, ISL89165
Contents
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
3.
4.
5.
5.1
5.2
5.3
5.4
6.
7.
8.
9.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
5
5
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Waveforms and Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
7
7
8
9
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Precision Thresholds for Time Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Paralleling Outputs to Double the Peak Drive Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation of the Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
15
15
General PCB Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General EPAD Heatsinking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FN7707 Rev.6.00
Jul.9.19
Page 2 of 22
ISL89163, ISL89164, ISL89165
1. Overview
1.
1.1
Overview
Block Diagram
VDD
For options A and B, the UV
comparator holds off the outputs
until V
DD
~> 3.3V
DC
. For option C,
the UV release is ~> 6.5V
Separate FET drives, with non-overlapping
outputs, prevent shoot-thru currents in the
output CMOS FETs resulting with very low
high frequency operating currents.
For clarity, only one channel is shown
ENx
ENx and INx inputs are identical and
may be interchanged for alternate logic
ISL89163
OUTx
INx
10k
ISL89164, ISL89165
EPAD
For proper thermal and electrical performance, the
EPAD must be connected to the PCB ground plane.
GND
Figure 3. Block Diagram
1.2
Ordering Information
Part
Marking
163A
163A
163B
163B
164A
164A
164B
164B
165A
165A
165B
165B
89163 FBEAZ
89163 FBEAZ
89163 FBEBZ
89163 FBEBZ
89164 FBEAZ
89164 FBEAZ
89164 FBEBZ
89164 FBEBZ
Temp
Range (°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
Inverting
Non-inverting
Inverting +
Non-inverting
Inverting
Input
Input
Tape and Reel
Configuration Logic (V) (Units) (Note
1)
Non-inverting
3.3
3.3
5.0
5.0
3.3
3.3
5.0
5.0
3.3
3.3
5.0
5.0
3.3
3.3
5.0
5.0
3.3
3.3
5.0
5.0
-
6k
-
6k
-
6k
-
6k
-
6k
-
6k
-
2.5k
-
2.5k
-
2.5k
-
2.5k
Package
(RoHS Compliant)
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
Pkg.
Dwg. #
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
Part Number
(Notes
2, 3, 4)
ISL89163FRTAZ
ISL89163FRTAZ-T
ISL89163FRTBZ
ISL89163FRTBZ-T
ISL89164FRTAZ
ISL89164FRTAZ-T
ISL89164FRTBZ
ISL89164FRTBZ-T
ISL89165FRTAZ
ISL89165FRTAZ-T
ISL89165FRTBZ
ISL89165FRTBZ-T
ISL89163FBEAZ
ISL89163FBEAZ-T
ISL89163FBEBZ
ISL89163FBEBZ-T
ISL89164FBEAZ
ISL89164FBEAZ-T
ISL89164FBEBZ
ISL89164FBEBZ-T
FN7707 Rev.6.00
Jul.9.19
Page 3 of 22
ISL89163, ISL89164, ISL89165
Part Number
(Notes
2, 3, 4)
ISL89165FBEAZ
ISL89165FBEAZ -T
ISL89165FBEBZ
ISL89165FBEBZ-T
Part
Marking
89165 FBEAZ
89165 FBEAZ
89165 FBEBZ
89165 FBEBZ
Temp
Range (°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
Input
Input
Tape and Reel
Configuration Logic (V) (Units) (Note
1)
Inverting +
Non-inverting
3.3V
3.3V
5.0V
5.0V
-
2.5k
-
2.5k
1. Overview
Package
(RoHS Compliant)
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
Pkg.
Dwg. #
M8.15D
M8.15D
M8.15D
M8.15D
Notes:
1. See
TB347
for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J-STD-020.
3. Input Logic Voltage: A = 3.3V, B = 5.0V.
4. For Moisture Sensitivity Level (MSL), see the
ISL89163, ISL89164, ISL89165
device pages. For more information about MSL, see
TB363.
Table 1.
Key Differences Between Family of Parts
I/O Pins
ENA
NINV
NINV
NINV
ENB
NINV
NINV
NINV
INA
NINV
INV
INV
INB
NINV
INV
NINV
OUTA
NINV
NINV
NINV
OUTB
NINV
NINV
NINV
Part Number
ISL89163
ISL89164
ISL89165
Note: INV: Inverting Input, NINV: Non-inverting input.
FN7707 Rev.6.00
Jul.9.19
Page 4 of 22
ISL89163, ISL89164, ISL89165
1. Overview
1.3
Pin Configurations
ISL89163FR, ISL89163FB
(8 Ld TDFN, EPSOIC)
Top View
ENA 1
INA 2
GND 3
INB 4
8 ENB
7 OUTA
6 VDD
5 OUTB
ISL89164FR, ISL89164FB
(8 Ld TDFN, EPSOIC)
Top View
ENA 1
/INA 2
GND 3
/INB 4
8 ENB
7 OUTA
6 VDD
5 OUTB
ISL89165FR, ISL89165FB
(8 Ld TDFN, EPSOIC)
Top View
ENA 1
/INA 2
GND 3
INB 4
8 ENB
7 OUTA
6 VDD
5 OUTB
1.4
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
Symbol
ENA
INA, /INA
GND
INB, /INB
OUTB
VDD
OUTA
ENB
EPAD
Channel A enable, 0V to VDD
Channel A input, 0V to VDD
Power Ground, 0V
Channel B enable, 0V to VDD
Channel B output
Power input, 4.5V to 16V
Channel A output, 0V to VDD
Channel B enable, 0V to VDD
Power Ground, 0V
Description
(See
Table 2)
Table 2.
ENx
INx
Truth Table for Logic Polarities
OUTx
ENx
/INx
Inverting
OUTx*
0
0
0
0
0
0
0
1
UV
0
0
0
0
1
1
1
1
ENx*
0
0
1
1
0
0
1
1
/INx*
0
1
0
1
0
1
0
1
OUTx*
0
0
0
0
0
0
1
0
OUTx
Non-Inverting
UV
0
0
0
0
1
1
1
1
ENx*
x
0
1
1
0
0
1
1
INx*
x
1
0
1
0
1
0
1
*Substitute A or B for x
FN7707 Rev.6.00
Jul.9.19
Page 5 of 22
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