ISP1501
Hi-Speed Universal Serial Bus peripheral transceiver
Rev. 02 — 21 November 2002
Product data
1. General description
The ISP1501 is a full-function transceiver designed to provide a Hi-Speed Universal
Serial Bus (USB) analog front-end to Application-Specific Integrated Circuits (ASICs)
and Field Programmable Gate Arrays (FPGAs) with a built-in USB Serial Interface
Engine (SIE). A Hi-Speed USB transceiver is integrated to implement USB
connectivity for high-speed peripherals. In addition, an Original USB transceiver
provides backward compatibility with full-speed USB systems. A minimum number of
external components is needed.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
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s
s
s
Complies with
Universal Serial Bus Specification Rev. 2.0
Legacy compliant Original USB full-speed transceiver interface
Bus-powered capability with suspend mode
Integrated parallel-to-serial converter (transmit) and serial-to-parallel converter
(receive) for Hi-Speed USB data
Hi-Speed USB data recovery upon receiving
Hi-Speed USB data synchronization upon transmitting
Integrated bit stuffing and de-stuffing for Hi-Speed USB data
Non-Return-to-Zero Inverted (NRZI) encoding and decoding for Hi-Speed
USB data
Integrated Phase Locked Loop (PLL) oscillator using 12 MHz crystal
Internal power-on reset
Separate 3.3 V supplies for analog transceiver and digital I/Os minimizes
crosstalk
3.3 V or 5 V tolerant digital input interface
16-bit bi-directional data bus allows FPGA verification, greatly reducing ASIC
implementation risk
Full industrial operating temperature range from
−40
to
+85 °C
6 kV in-circuit ESD protection; compliant with
IEC 61000-4-2
(level 3)
Available in LQFP48 package.
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
3. Applications
s
Scanner
s
Digital still camera
s
Printer, e.g.
x
Color printer
x
Multi-functional printer
s
External storage device, e.g.
x
Portable hard disk
x
Zip
®
drive
x
Jaz
®
drive
x
Magneto-optical (MO) drive
x
Optical drive (CD-ROM, CD-RW, DVD).
4. Ordering information
Table 1:
Ordering information
Package
Name
ISP1501BE
LQFP48
Description
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
Version
SOT313-2
Type number
9397 750 10025
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 21 November 2002
2 of 40
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
5. Block diagram
CLKOUT48
CLKOUT30
MODE0, MODE1
RESET
SUSPEND
TX_VALID/OE
2
13
15
11, 12
3
1
2
7
HIGH-SPEED
TRANSCEIVER
NZRI
+
BS
ENCODER
6
SYSTEM LOGIC
ISP1501
9
RPU
TX_READY
TX_BS_EN/FSE0
TX_LAST_BYTE
DDIR
43
44
42
20
DP
DM
16
DATA15 to DATA0
38 to 31,
28 to 21
RX_VALID/VP
RX_INACTIVE/VM
RX_BS_ERROR/RCV
RX_LAST_BYTE
48
47
46
39
NZRI
+
BS
DECODER
FULL-SPEED
TRANSCEIVER
TEST_J_K/VO
VCCA1 to VCCA3
VCCD1, VCCD2
DGND1, DGND2
AGND1 to AGND3
3
2
2
3
45
5, 8, 16
29, 40
30, 41
4, 10, 19
POWER
SUPPLY
PLL
OSCILLATOR
18
17
XTAL1
XTAL2
MGT059
Fig 1. Block diagram.
9397 750 10025
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 21 November 2002
3 of 40
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
6. Pinning information
6.1 Pinning
idth
46 RX_BS_ERROR/RCV
47 RX_INACTIVE/VM
44 TX_BS_EN/FSE0
39 RX_LAST_BYTE
42 TX_LAST_BYTE
45 TEST_J_K/VO
48 RX_VALID/VP
43 TX_READY
38 DATA15
37 DATA14
41 DGND2
40 VCCD2
SUSPEND 1
TX_VALID/OE 2
RESET 3
AGND1 4
VCCA1 5
DM 6
DP 7
VCCA2 8
RPU 9
AGND2 10
MODE0 11
MODE1 12
36 DATA13
35 DATA12
34 DATA11
33 DATA10
32 DATA9
ISP1501BE
31 DATA8
30 DGND1
29 VCCD1
28 DATA7
27 DATA6
26 DATA5
25 DATA4
CLKOUT48 13
CLKOUT30 15
VCCA3 16
AGND3 19
DATA1 22
DATA3 24
DATA0 21
RREF 14
XTAL2 17
XTAL1 18
DDIR 20
DATA2 23
MGT060
Fig 2. Pin configuration LQFP48.
6.2 Pin description
Table 2:
Symbol
[1]
SUSPEND
TX_VALID/
OE
Pin description
Pin
1
2
Type
I
I
Description
enables power saving mode for USB suspend state
pin function depends on operating mode (see
Table 3):
State = 0, 1 —
output enable for FS transceiver
[2]
State = 2, 3 —
transmission valid flag for HS transceiver
[2]
RESET
AGND1
V
CCA1
DM
3
4
5
6
I
-
-
AI/O
reset input
analog ground 1 supply
analog supply voltage 1 (3.3 V)
USB D− connection (analog) with integrated 45
Ω
series
resistor
9397 750 10025
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 21 November 2002
4 of 40
Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Pin description
…continued
Pin
7
8
9
Type
AI/O
-
AI
Description
USB D+ connection (analog) with integrated 45
Ω
series
resistor
analog supply voltage 2 (3.3 V)
connection for external pull-up resistor (1.5 kΩ
±
5%) on
USB D+; switched on via internal switch during the FS and
HS chirp states
analog ground 2 supply
operating state and interface selection input 0; see
Table 3
operating state and interface selection input 1; see
Table 3
48 MHz clock output; clock is always running when input
SUSPEND is logic 0; see
Section 17
on application of this
clock
connection for external reference resistor (12 kΩ
±
1%) to
analog ground supply
clock output for Hi-Speed USB digital interface (30 MHz);
clock is always running when input SUSPEND is logic 0
analog supply voltage 3 (3.3 V)
crystal oscillator output (12 MHz)
crystal oscillator input (12 MHz)
analog ground 3 supply
selects direction of 16-bit data bus DATA[15:0]
data bit 0; bi-directional, slew rate controlled output (5 ns)
data bit 1; bi-directional, slew rate controlled output (5 ns)
data bit 2; bi-directional, slew rate controlled output (5 ns)
data bit 3; bi-directional, slew rate controlled output (5 ns)
data bit 4; bi-directional, slew rate controlled output (5 ns)
data bit 5; bi-directional, slew rate controlled output (5 ns)
data bit 6; bi-directional, slew rate controlled output (5 ns)
data bit 7; bi-directional, slew rate controlled output (5 ns)
digital supply voltage 1 (3.3 V)
digital ground 1 supply
data bit 8; bi-directional, slew rate controlled output (5 ns)
data bit 9; bi-directional, slew rate controlled output (5 ns)
data bit 10; bi-directional, slew rate controlled output (5 ns)
data bit 11; bi-directional, slew rate controlled output (5 ns)
data bit 12; bi-directional, slew rate controlled output (5 ns)
data bit 13; bi-directional, slew rate controlled output (5 ns)
data bit 14; bi-directional, slew rate controlled output (5 ns)
data bit 15; bi-directional, slew rate controlled output (5 ns)
logic 0 —
DATA[7:0] = valid data, DATA[15:8] = valid data
logic 1 —
DATA[7:0] = valid data, DATA[15:8] = bit stuff
error byte
Table 2:
Symbol
[1]
DP
V
CCA2
RPU
AGND2
MODE0
MODE1
CLKOUT48
10
11
12
13
-
I
I
O
RREF
CLKOUT30
V
CCA3
XTAL2
XTAL1
AGND3
DDIR
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
V
CCD1
DGND1
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
RX_LAST_BYTE
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
AI
O
-
AO
AI
-
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
V
CCD2
9397 750 10025
40
-
digital supply voltage 2 (3.3 V)
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 21 November 2002
5 of 40
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