®
ISL6594A, ISL6594B
Data Sheet
May 2004
FN9157
Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features
The ISL6594A and ISL6594B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with the
ISL6592 Digital Multi-Phase Buck PWM controller and
N-Channel MOSFETs form a complete core-voltage
regulator solution for advanced microprocessors.
The ISL6594A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The ISL6594B drives both upper and lower gates over
a range of 5V to 12V. This drive-voltage provides the
flexibility necessary to optimize applications involving trade-
offs between gate charge and conduction losses.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. These products add an overvoltage protection feature
operational before VCC exceeds its turn-on threshold, at
which the PHASE node is connected to the gate of the low
side MOSFET (LGATE). The output voltage of the converter
is then limited by the threshold of the low side MOSFET,
which provides some protection to the microprocessor if the
upper MOSFET(s) is shorted during initial startup.
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
Features
• Pin-to-pin Compatible with HIP6601 SOIC family for Better
Performance and Extra Protection Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- Auto-zero of r
DS(ON)
Conduction Offset Effect
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Finish Option for Environmental Regulations
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC-DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Briefs TB400 and TB417 for Power Train
Design, Layout Guidelines, and Feedback Compensation
Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6594A, ISL6594B
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
ISL6594ACB
ISL6594ACB-T
ISL6594AECB
ISL6594AECB-T
ISL6594ACR
ISL6594ACR-T
ISL6594BCB
ISL6594BCB-T
ISL6594BECB
ISL6594BECB-T
ISL6594BCR
ISL6594BCR-T
ISL6594ACBZ*
ISL6594ACBZ-T*
0 to 85
PACKAGE
8 Ld SOIC
PKG.
DWG. #
M8.15
Ordering Information
(Continued)
TEMP.
PART NUMBER RANGE (°C)
ISL6594AECBZ*
0 to 85
PACKAGE
8 Ld EPSOIC (Pb-Free)
PKG.
DWG. #
M8.15B
8 Ld SOIC Tape and Reel
0 to 85
8 Ld EPSOIC
M8.15B
ISL6594AECBZ-T* 8 Ld EPSOIC Tape and Reel (Pb-Free)
ISL6594ACRZ*
ISL6594ACRZ-T*
L10.3x3
0 to 85
10 Ld 3x3 DFN (Pb-Free)
L10.3x3
8 Ld EPSOIC Tape and Reel
0 to 85
10 Ld 3x3 DFN
10 Ld 3x3 DFN Tape and Reel (Pb-Free)
0 to 85
8 Ld SOIC (Pb-Free)
M8.15
ISL6594BCBZ*
ISL6594BCBZ-T*
10 Ld 3x3 DFN Tape and Reel
0 to 85
8 Ld SOIC
M8.15
8 Ld SOIC Tape and Reel (Pb-Free)
0 to 85
8 Ld EPSOIC (Pb-Free)
M8.15B
ISL6594BECBZ*
8 Ld SOIC Tape and Reel
0 to 85
8 Ld EPSOIC
M8.15B
ISL6594BECBZ-T* 8 Ld EPSOIC Tape and Reel (Pb-Free)
ISL6594BCRZ*
ISL6594BCRZ-T*
L10.3x3
0 to 85
10 Ld 3x3 DFN (Pb-Free)
L10.3x3
8 Ld EPSOIC Tape and Reel
0 to 85
10 Ld 3x3 DFN
10 Ld 3x3 DFN Tape and Reel (Pb-Free)
10 Ld 3x3 DFN Tape and Reel
0 to 85
8 Ld SOIC (Pb-Free)
M8.15
8 Ld SOIC Tape and Reel (Pb-Free)
* Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J Std-020B.
Pinouts
ISL6594ACB, ISL6594BCB (SOIC)
ISL6594AECB, ISL6594BECB (EPSOIC)
TOP VIEW
UGATE
BOOT
PWM
GND
1
2
3
4
GND
8
7
6
5
PHASE
PVCC
VCC
LGATE
ISL6594ACR, ISL6594BCR (10L 3x3 DFN)
TOP VIEW
UGATE
BOOT
N/C
PWM
GND
1
2
3
4
5
GND
10 PHASE
9 PVCC
8
7
N/C
VCC
6 LGATE
Block Diagram
ISL6594A AND ISL6594B
UVCC
VCC
+5V
10K
PWM
POR/
CONTROL
8K
LOGIC
OTP AND
Pre-POR OVP
FEATURES
BOOT
UGATE
PHASE
(LVCC)
PVCC
SHOOT-
THROUGH
PROTECTION
UVCC = VCC FOR ISL6594A
UVCC = PVCC FOR ISL6594B
LGATE
GND
PAD
FOR DFN AND EPSOIC-DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
2
Typical Application - 4 Channel Converter Using ISL6592 and ISL6594A Gate Drivers
+12V
+5V
ISL6594
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
3
+3.3V
VDD
V12_SEN
GND
ISL6594
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
ISL6592
VID4
VID3
VID2
VID1
FROM µP
VID0
VID5
LL0
LL1
OUTEN
OUT1
OUT2
ISEN1
OUT3
OUT4
ISEN2
OUT5
OUT6
ISEN3
OUT7
OUT8
ISL6594A, ISL6594B
LGATE 5
ISL6594
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
Vout
TO µP
VCC_PWRGD
ISEN4
OUT9
RTN
RESET_N
OUT10
ISEN5
ISL6594
1 UGATE
2 BOOT
3 PWM
4 GND
PHASE 8
PVCC 7
VCC 6
LGATE 5
FAULT
OUTPUTS
FAULT1
FAULT2
OUT11
OUT12
ISEN6
SDA
I2C I/F
BUS
SCL
SADDR
TEMP_SEN
CAL_CUR_EN
CAL_CUR_SEN
VSENP
VSENN
RTHERM
ISL6594A, ISL6594B
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (V
BOOT
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (V
PWM
) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . V
PHASE
- 0.3V
DC
to V
BOOT
+ 0.3V
V
PHASE
- 3.5V (<100ns Pulse Width, 2µJ) to V
BOOT
+ 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V
DC
to V
PVCC
+ 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to V
PVCC
+ 0.3V
PHASE. . . . . . . . . . . . . . . GND - 0.3V
DC
to 15V
DC
(V
PVCC
= 12V)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, V
BOOT-PHASE
= 12V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
θ
JA
(°C/W)
θ
JC
(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . .
100
N/A
EPSOIC Package (Notes 2, 3). . . . . . .
50
7
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V
±10%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air.
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
ISL6594A, f
PWM
= 300kHz, V
VCC
= 12V
ISL6594B, f
PWM
= 300kHz, V
VCC
= 12V
-
-
-
-
-
-
-
-
7.2
4.5
11
5
2.5
5.2
7
13
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
I
VCC
ISL6594A, f
PWM
= 1MHz, V
VCC
= 12V
ISL6594B, f
PWM
= 1MHz, V
VCC
= 12V
Gate Drive Bias Current
I
PVCC
ISL6594A, f
PWM
= 300kHz, V
PVCC
= 12V
ISL6594B, f
PWM
= 300kHz, V
PVCC
= 12V
I
PVCC
ISL6594A, f
PWM
= 1MHz, V
PVCC
= 12V
ISL6594B, f
PWM
= 1MHz, V
PVCC
= 12V
POWER-ON RESET AND ENABLE
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT (See Timing Diagram on Page 6)
Input Current
I
PWM
V
PWM
= 3.3V
V
PWM
= 0V
PWM Rising Threshold
PWM Falling Threshold
Typical Three-State Shutdown Window
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
-
-
-
-
1.23
-
-
-
450
-400
1.70
1.30
-
1.18
0.76
2.36
-
-
-
-
1.82
-
-
-
µA
µA
V
V
V
V
V
V
9.35
7.35
9.80
7.60
10.00
8.00
V
V
4
ISL6594A, ISL6594B
Electrical Specifications
PARAMETER
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT
Upper Drive Source Current (Note 4)
Upper Drive Source Impedance
Upper Drive Sink Current (Note 4)
Upper Drive Sink Impedance
Lower Drive Source Current (Note 4)
Lower Drive Source Impedance
Lower Drive Sink Current (Note 4)
Lower Drive Sink Impedance
NOTE:
4. Guaranteed by design. Not 100% tested in production.
I
U_SOURCE
V
PVCC
= 12V, 3nF Load
R
U_SOURCE
150mA Source Current
I
U_SINK
R
U_SINK
I
L_SOURCE
V
PVCC
= 12V, 3nF Load
150mA Sink Current
V
PVCC
= 12V, 3nF Load
-
1.4
-
0.9
-
0.85
-
0.60
1.25
2.0
2
1.65
2
1.3
3
0.94
-
3.0
-
2.85
-
2.2
-
1.35
A
Ω
A
Ω
A
Ω
A
Ω
t
TSSHD
t
RU
t
RL
t
FU
t
FL
t
PDHU
t
PDHL
t
PDLU
t
PDLL
t
PDTS
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load, Adaptive
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
TEST CONDITIONS
VCC = 12V
MIN
-
-
-
-
-
-
-
-
-
-
-
TYP
1.96
245
26
18
18
12
10
10
10
10
10
MAX
-
-
-
-
-
-
-
-
-
-
-
UNITS
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L_SOURCE
150mA Source Current
I
L_SINK
R
L_SINK
V
PVCC
= 12V, 3nF Load
150mA Sink Current
Functional Pin Description
PACKAGE PIN #
SOIC
1
2
DFN
1
2
PIN
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
No Connection.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives in ISL6594B; only the lower gate drive in ISL6594A.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
-
3
3,8
4
N/C
PWM
4
5
6
7
8
9
5
6
7
9
10
11
GND
LGATE
VCC
PVCC
PHASE
PAD
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
