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OCTOBER 1993
ADVANCE INFORMATION
DS3307-2·3
MV3100
3 VOLT CODEC WITH ANALOG INTERFACE FOR DIGITAL MOBILE TELEPHONES
(Supersedes version in June 1990 Personal Communications IC Handbook)
The MV3100 is a complete integrated audio interface for
digital mobile telehones.Using mixed signal CMOS technology
the device contains a DSP codec for audio to PCM conversion,
together with gain programmable microphone and loudspeaker
amplifiers.
The use of a DSP architecture for the codec function enables
device operation from supplies of 2·7 to 3·6 volts and allows
software programming of gain characteristics.The device re-
quires a minimum of external components giving a physically
small solution, ideal for hand-portable telephones.
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
17
18
19
20
21
22
MV3100
44
43
42
41
40
39
38
37
36
35
34
FEATURES
s
Highly Integrated Solution with On-chip Audio Interface
s
Meets Relevant Performance Parameters from
MPT1375, I-ETS 300 131:1990, BS6833 and CCITT G714
s
Low Voltage Operation, 2·7V to 3·6V
s
Low Power Consumption, 25mW typ
s
Excellent RF Immunity
s
16-Bit Linear/8-Bit Companded A/µ-Law
Programmable PCM Interface
s
Gain Programmability Supports many Microphone and
Loudspeaker Sensitivities
s
On-chip PLL Generates all Internal Clocks
GP44
Fig.1 Pin connections - top view. See pin list, Table 1.
APPLICATIONS
s
Digital Cordless Telephones (CT2, DECT, JDCT,
Spread Spectrum)
s
Digital Cellular Telephones (GSM, ADC, JDC)
s
Digital Mobile Radio
ORDERING INFORMATION
MV3100 IG GPBR
(Industrial - plastic QFP package)
MICROPHONE
AMPLIFIER
MICIN1
MICIN2
4
6
1
BUFFER
AMPLIFIER
IN
23
24
25
26
27
28
29
30
31
32
33
2
AUXOUT
2
V
REF
CTL
LOUDSPEAKER
AMPLIFIER
LSOPP
LSOPN
12
1
13
2
V
REF
CTL
ANTI-ALIAS
FILTER
CTL
SIGMA-DELTA
CODER
DECIMATOR
27
TXOUT
V
REF
LSC1
9
29
V
REF
CTL
V
REF
CTL
CTL
SIGNAL
PROCESSOR
PCM
INTERFACE
28
FS
SUMMING
AMPLIFIER
ST
BCLK
LSC2
8
IN
AUX
RECONSTRUCTION
FILTER
DAC
INTERPOLATOR
30
RXIN
AUXIN
CD0
CD1
FIN
(MASTER
CLOCK)
7
41
42
38
V
REF
CTL
V
REF
CTL
V
REF
CTL
CTL
CTL
CTL
18
DATA
ENABLE
CLOCK
RESET
PLL
CLOCK
V
REF
V
REF
CTL
CTL
CONTROL
REGISTERS
17
16
14
V
REF
CTL
44
VRDC
Fig. 2 MV3100 block diagram
MV3100
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
V
DD
TX
AUXOUT
IC
MICIN1
GNDTX
MICIN2
AUXIN
LSC2
LSC1
GNDRX
V
DD
RX
LSOPP
LSOPN
RESET
IC
CLOCK
ENABLE
DATA
IC
IC
IC
IC
IC
NC
V
DD
D
NC
TXOUT
BCLK
FS
RXIN
GNDD
NC
IC
NC
IC
IC
IC
FIN
V
DD
PL
GNDPL
CD0
CD1
NC
VRDC
Description
Transmit path analog V
DD
Transmit path auxiliary output
Internal connection - do not connect
Microphone amp. input non-inverting input
Transmit path analog ground
Microphone amp. inverting input
Receive path auxiliary input
Summing amplifier intermediate output
Loudspeaker amplifier intermediate input
Receive path analog ground
Receive path analog V
DD
Loudspeaker amp. non-inverting output
Loudspeaker amp. inverting output
Master reset (active low)
Internal connection - do not connect
Control interface data clock
Control interface enable
Control interface data input
Internal connection - do not connect
Internal connection - do not connect
Internal connection - do not connect
Internal connection - do not connect
Internal connection - do not connect
No connection
Digital V
DD
No connection
PCM interface transmit data output
PCM interface data clock
PCM interface frame sync.
PCM interface receive data input
Digital ground
No connection
Internal connection - do not connect
No connection
Internal connection - do not connect
Internal connection - do not connect
Internal connection - do not connect
PLL reference frequency input (Master Clock)
PLL V
DD
PLL ground
PLL capacitor ground connection
PLL capacitor signal connection
No connection
Voltage reference decoupling
transmit filter has reduced bass roll-off.
The filtered digital transmit signal from the Signal Processor
is output via the serial PCM interface. The PCM interface can be
programmed via the control interface to operate in one of three
modes, 16-bit 2's complement linear PCM, 8-bit companded A-
Law coding or 8-bit companded
µ-Law
coding. In all modes, each
word or byte is output as a serial bit stream at a frame rate of 8K
words/bytes per second under the control of the bit clock BCLK
and the frame sync FS inputs. A mute function is included on the
output.
The digital receive signal is input to the Signal Processor via
the PCM interface as a series of sixteen-bit words or eight-bit
bytes as described above. A separately controlled mute function
may also be applied.
The Signal Processor performs the receive band-pass filter-
ing and then passes the filtered digital signal to the Interpolator.
The Interpolator in conjunction with the DAC performs a high
linearity digital to analog conversion. The resulting analog output
is filtered by the Reconstruction Filter to remove the sampling
noise.
The Summing Amplifier may optionally add to the received
signal the auxiliary analog input and the sidetone signal from the
transmit path. The nominal sidetone gain may be varied from
19·7 dB to 28·7 dB in 3dB steps. The Summing Amplifier output
is connected externally to the Loudspeaker Amplifier input to
enable external filtering components to be added if required. The
Loudspeaker Amplifier is a bridge amplifier which has been
designed to drive a ceramic loudspeaker. It can produce a low
distortion drive into loads of up to 105nF at a peak to peak
amplitude near to twice V
DD
.
The Phase Locked Loop generates the internal clock signals
from a 32kHz input clock. After power-up the PLL clock must be
enabled by programming Control Register 100 bit 3 (PLL Clock
Enable) to the on state (‘0’).The PLL is specifically designed to
extract a low phase error clock in cases where there is jitter on
the input clock, provided that there are exactly 64 input clock
cycles in every 500Hz period. This ensures accurate clock
extraction from the CT2 ‘ping-pong’ signalling system.
The on-chip bandgap voltage reference provides the neces-
sary biasing and reference voltages required by the analog
circuitry.
Programming of the various gains and operating modes for
the device is by means of a three-wire serial interface to the
Control Registers. Data is clocked into the Data input under
control of the Clock and Enable inputs. The digital circuitry and
various parts of the analog circuitry may be powered down
individually by means of the control interface. This may be used
to minimise power consumption during various phases of call
set-up and standby operation.
The device is designed to operate from a nominal 3 volt
supply. Separate supply and ground pins are provided for the
transmit analog, receive analog and digital circuits to improve
decoupling between transmit and receive paths and reduce
digital noise breakthrough into the analog circuitry.
Table 1 Pin list
FUNCTIONAL DESCRIPTION
The transmit circuit has a low noise differential input micro-
phone amplifier front end and is suitable for use with an electret
microphone. For use in cordless or mobile telephone applica-
tions the sensitive analog inputs are designed to be immune to
RF pickup. The transmit gain may be varied over a range of 22·8
dBm0/dBV to 37·8 dBm0/dBV in 1dB steps. An auxiliary analog
output is available.
The analog transmit signal is passed through a simple Anti-
alias Filter and is then sampled by the Sigma-Delta Coder which,
combined with the Decimator, performs a high linearity analog to
digital conversion. This digital signal is then passed to the Signal
Processor which performs the transmit filtering. The transmit
filter may be set to either of two modes. For handset use the full
band-pass filter is implemented, while for base station use the
DETAILED DESCRIPTION
Microphone Input
The Microphone Amplifier was designed to meet the CT2
Common Air Interface specification MPT1375 Part 4. With the
transmit gain set to its nominal value, an input of
234·8dBV
will
produce a digital output of 0 dBm0. The circuit was designed for
a microphone with a nominal sensitivity of
241·8dBV/Pa.
This
gain may be varied by
13·0dB
to
212·0dB
in steps of 1dB by
means of the control interface. This gain range is intended to
provide for a microphone sensitivity tolerance of
63
dB and permits
a gain reduction of up to 9dB to reduce sensitivity for use in
conditions of high ambient noise.
The Microphone Amplifier may be powered down by means
of the control interface when not in use to reduce power
consumption.
2
MV3100
Auxiliary Output
The auxiliary output has a nominal gain of 19·9 dB from the
microphone input. The output level is dependent on the gain
setting giving a gain range of 7·9dB to 22·9dB. The output is
designed to be able to deliver a 500 mV rms signal into a 30kΩ
120
pF load.
The auxiliary output may be turned off by means of the control
interface when not in use to reduce power consumption.
Loudspeaker Output
The Loudspeaker Amplifier was designed to meet the CT2
Common Air Interface specification MPT1375 Part 4. With the
receive gain set to its nominal value, an output of
26·1dBV
will
be produced for a digital input of 0dBm0. The circuit was
designed for a loudspeaker with a nominal sensitivity of
112·0
dBPa/V. The gain may be varied by
19·0dB
to
222·0dB
in steps
of 1dB by means of the control interface. This gain range is
intended to provide for a loudspeaker sensitivity tolerance of
6
3dB and permit a gain variation of
16dB
to218dB to enable
the implementation of a user volume control.
The Loudspeaker Amplifier may be powered down when not
in use by means of the control interface to reduce power
consumption.
The nominal gain from the auxiliary input to the loudspeaker
output is 13·4dB. This gain is dependent on the receive gain
setting giving a gain range of
122·4dB
to28·6dB. The auxiliary
input may be disconnected by means of the control interface if
not required.
The nominal sidetone gain from the microphone input to the
loudspeaker output (with both transmit and receive gains set to
nominal) is 25·7dB. This gain may be varied by
13·0dB
to
26·0dB
in 3·0dB steps by means of the control interface. If not
required, the sidetone may be turned off by means of the control
interface.
The serial PCM interface thus consists of four pins; three
inputs and one output.
BCLK PCM data clock input
FS
PCM frame sync input
TXOUT PCM transmit data output
RXIN
PCM receive data input
Interface timings are shown in Figs. 3 and 4.
NOTES
1. The Sync pulse is nominally one clock pulse wide, changes in
state nominally coinciding with the rising edge of the clock. Jitter
on the FS rising edge can occur up to
65µs
on the actual and
ideal edge positions.
2. The Data bits are nominally one clock cycle wide, nominally
changing on the rising edge of the clock.
3. Data bits (RXIN) will be latched nominally on the falling edge
of the clock.
4. The data output (TXOUT) will be high impedance between the
end of the last data bit of one word/byte and the beginning of the
first data bit of the next word/byte.
5. The RXIN signal must always be at a solid logic level, even
though it is only the data at the times indicated which is used. In
the case of RXIN the mid-line should be taken to indicate a ‘don’t
care’ state, not a high impedance state.
6. The Clock signal BCLK may consist of either a train of at least
seventeen pulses in linear PCM mode or nine pulses in A/µ-Law
companded PCM mode (one for FS and one for each data bit),
or be a continuous clock.
This block is the interface between parallel 2's complement
sixteen-bit linear PCM data and serial sixteen- bit linear 2's
complement or serial eight-bit A/µ-Law companded PCM data,
performing parallel-to-serial conversion in the transmit direction
and serial-to-parallel conversion in the receive direction. In
addition to the conversion and coding function the PCM block
implements a mute function. Both TX and RX can be independ-
ently muted. The mute functions are controlled from the micro-
processor bus control interface.
PCM INTERFACE
The PCM Interface inputs the received digital signal RXIN
and outputs the transmit digital signal TXOUT in the form of
sixteen-bit words or eight-bit bytes as a serial bit stream under
the control of the two timing signals FS and BCLK.
Three PCM coding options are programmable via the control
interface, linear sixteen-bit 2's complement PCM, eight-bit A-
Law companded PCM or eight bit
µ-Law
companded PCM. It is
normal in a system to have a single coding scheme; for this
reason Transmit and Receive coding are programmed simulta-
neously to work with the same scheme.
t
SYN
FS
t
BCKH
BCLK
RXIN
OR
TXOUT
MSB
A-Law and
µ-Law
Codes (8 Bit)
These are non-linear codes in which the signal is described
in terms of a sign bit plus segment and chord bits which denote
the magnitude. There are 7 segments for A- Law and 8 for
µ-Law.
The size of the segment increases in approximately exponential
steps. Each segment is divided up linearly into chords (except
the zero level in
µ-Law).
This means that the resolution is finer
at smaller input voltages than at larger. Tables detailing these
t
BCKL
16-BIT LINEAR
/
8-BIT COMPANDED
Fig. 3 PCM Interface timing diagram
Value
Parameter
BCLK frequency (linear mode)
BCLK frequency (companded mode)
BCLK rise time
BCLK fall time
BCLK high time
BCLK low time
FS pulse period
Symbol
f
BCK
f
BCK
t
BCKR
t
BCKF
t
BCKH
t
BCKL
t
SYN
Min.
256
128
5
5
200
200
125
Typ.
Max.
2048
2048
Units
kHz
kHz
ns
ns
ns
ns
µs
Conditions
FIN = 32kHz
NOTE 1: The Frame Sync (FS) MUST be frequency locked to the 32kHz PLL Master Clock (FIN). The phase relationship is not important.
Table 2 PCM Interface timings
MSB
LSB
3
MV3100
FS
t
SR
BCLK
t
DZH
t
DZL
TXOUT
t
RSU
RXIN
MSB
t
SSU
t
SH
t
SF
t
DLH
t
DHL
MSB
t
DHZ
t
DLZ
LSB
t
RH
LSB
Fig. 4 PCM Interface timing diagram (expanded)
Value
Parameter
FS to BCLK set-up time
FS to BCLK hold time
BCLK to FS rising time
FS falling to BCLK time
Output delay from Z to high
Output delay from Z to low
Output delay from high to Z
Output delay from low to Z
Output delay from high to low
Output delay from low to high
RXIN set-up time
RXIN hold time
NOTE 2. Not production tested
Symbol
Min.
Typ.
Max.
Units
Conditions
Notes
2
2
2
2
2
2
2
2
2
2
t
SSU
10
ns
ns
15
t
SH
ns
25
t
SR
ns
25
t
SF
25
t
DZH
ns
25
ns
t
DZL
25
ns
t
DHZ
25
ns
t
DLZ
30
t
DHL
ns
30
ns
t
DLH
ns
10
t
RSU
ns
15
t
RH
Table 3 PCM Interface timings (see Fig. 4)
codes can be found in CCITT G711.
In both codes positive values are represented by a sign bit of
1. The A-Law data is alternate digit inverted (ADI) and the
µ-Law
magnitude data is in effect inverted. These techniques are used
to ensure that there are sufficient data transitions for good clock
recovery (not performed by the MV3100) on the Received side
of the digital trunk lines when the channel is quiet.
The data is serially clocked into the DATA input by the
CLOCK input. The first 5 bits are the data to be stored and the
second 3 bits identify which register is to be addressed. After the
data has been clocked in, a separate ENABLE pulse stores the
data in the appropriate register.
The Control Interface has four inputs:
CLOCK
Control Interface clock
DATA
Serial data input for the control registers
ENABLE
Control Interface enable Signal
RESET
See below
The RESET input is used to provide a full chip reset. The
general rule is that, on reset, the chip is set to handset
operation, minimum gain settings and all parts powered
down, with the exception of the PLL and the V
REF
(CR0<1>)
which is powered up.
CONTROL INTERFACE (SEE FIGS. 5 AND 6))
The Control Interface essentially has two sections. Firstly the
serial/parallel input shift and address decode section, which
controls the control registers. This is the Control Interface proper.
Secondly, the reset section which generates a digital chip reset
from the combination of ‘hard’ (i.e., power-on/pin generated)
and ‘soft’ (i.e., programmed into the control registers) resets.
CLOCK
t
DSU
DATA
XX
D0
D1
D2
t
DH
D3
D4
A0
A1
t
CE1
A2
t
CE2
XXXXXXXXXXXXXXXXXXXXXXXXXXXX
t
ENW
ENABLE
t
PED
LATCHED
DATA
PREVIOUS DATA
NEW DATA
Fig. 5 Control Interface timing diagram
4
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