MV1820
Purchase of Mitel Semiconductor I
2
C components conveys a licence under the Philips
I
2
C Patent rights to use these components in an I
2
C System, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
HEADQUARTERS OPERATIONS
MITEL SEMICONDUCTOR
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (01793) 518000
Fax: (01793) 518411
MITEL SEMICONDUCTOR
1500 Green Hills Road,
Scotts Valley, California 95066-4922
United States of America.
Tel (408) 438 2900
Fax: (408) 438 5576/6231
Internet: http://www.gpsemi.com
CUSTOMER SERVICE CENTRES
G
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These are supported by Agents and Distributors in major countries world-wide.
© Mitel Corporation 1998 Publication No. DS3106 Issue No. 3.0 May 1996
TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any
guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and
to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
6
MV1820
CRYSTAL SPECIFICATION
Parallel resonant fundamental frequency 27.750000MHz. AT cut.
Tolerance at -10°C to 60°C
±
50ppm.
Tolerance overall
±
100ppm.
Nominal load capacitance 20pF.
Equivalent series resistance <20Ω.
FUNCTIONAL DESCRIPTION
The video signal is sliced to produce data and
synchronising signals. Timing circuits monitor the sync signal
to enable the MV1820 to lock onto the broadcast signal. A
timing window, for the Vertical Blanking Interval (VBI) lines 6
- 22 and 318 - 335, is established to enable the acquisition
circuit to monitor the sliced data signal for valid teletext data.
The framing code is checked for valid World System
Teletext (WST) data. Magazine, packet and designation code
bytes are checked and valid Broadcast Service Data Packets
(BSDP) format two type only are accepted. These are known
as packet 8/30. Format two is signalled by byte six, data bit two
being set high and bits 3 and 4 set low. Bytes 13 to 25 inclusive
are Hamming decoded (8,4) and stored in seven registers
each of eight bits. If the complete message is correctly
received with no uncorrectable Hamming errors, an interrupt
to the microprocessor is signalled by the DAV (bar) pin going
low. At the same time the data is transferred to a second bank
of registers, reorganised with original numbered bytes 14, 15,
24, 25 and 13 placed after byte 23, to be read out on the I
2
C
bus when so requested. Subsequent valid messages will
continue to be transferred to the output registers overwriting
any existing data. In this way the output registers always
contain the latest PDC message.
The MV1820 is configured as an I
2
C bus slave transmitter
with a selectable address. The I
2
C bus address is 0010 0001
(20 + 1 hex) with the address select (AS) pin set high, or 0010
0011 (22 + 1 hex) with the AS pin set low. The read bit (LSB)
must always be set, it is not possible to write to the MV1820.
On recognising its address, the MV1820 will send an
acknowledge and then transmit on the SDA line the first byte
from the output registers (decoded byte 16 and 17) most
significant bit (MSB) first. It will then monitor the SDA line for
an acknowledge from the microprocessor. If the
microprocessor does NOT send an acknowledge, the
MV1820 will release the data line to allow the microprocessor
to send a stop condition. If the microprocessor does send an
acknowledge, the following bytes of the message will be
output provided each byte is acknowledged. The final data will
be byte 13 followed by the four ‘1’s.
When readout is complete, the DAV (bar) pin is reset high
and the output registers are all set high. If the microprocessor
continues to send clocks on the SCL line, the MV1820 will
output FF bytes on the SDA line. Also, if the MV1820 is re-
addressed before another PDC message is received, the
MV1820 will output FF bytes on the SDA line. The
microprocessor can prematurely stop the message by NOT
sending an Acknowledge followed by a STOP condition after
any byte has been sent by the MV1820. The registers will then
be reset to FF bytes and the DAV pin will be reset high.
To prevent any corruption of the data in the output
registers during I
2
C bus activity, valid PDC messages are held
in the incoming registers until I
2
C bus activity ceases. Here
they may be overwritten by new PDC messages until the I
2
C
bus activity ceases and they can then be transferred to the
output registers.
System clock is provided by an on - chip 27.75MHz
oscillator together with an external parallel resonant
fundamental frequency AT cut crystal.
Following a reset, RESET pulled low, the output I
2
C bus
registers will contain FF bytes and the DAV pin will be set high.
When the power supply is removed, the I
2
C bus will not be
clamped to ground, leaving it free for other I
2
C bus traffic.
Fig.3 Typical application diagram
4
MV1820
ELECTRICAL CHARACTERISTICS (continued)
These characteristics are guaranteed over the following conditions (unless otherwise stated)
T
amb
= 0 to 70˚C, V
DD
= 5V
±
10%
Characteristic
I2C bus
SCL, SDA Schmitt inputs
Input voltage Low
Input voltage High
Output voltage Low
SCL clock frequency
DAV data available
Output voltage low
RESET Schmitt input
Input voltage Low
Input voltage High
Input current Low
Input current High
1
0
V
DD
-1.0
-22
-10
-50
0.8
V
DD
-220
+10
V
V
µA
µA
V
IN
= V
SS
V
IN
= V
DD
0.2
0.4
V
11
11, 13
0
3.5
0.1
100
1.5
V
DD
0.4
1000
V
V
V
kHz
100k (nom) pull-up resistor
I
OH
= 2.4mA
100k (nom) pull-up resistor
I
OL
= 3.0mA
Not clamped when V
DD
= 0V
Pin
Value
Min
Typ
Max
Units
Conditions
NOTE
Input voltage low and input voltage high for EXT/INT, AS and XTI are as specified for DATA I/O.
PIN DESCRIPTION
Symbol
RESET
EXT/INT
Pin
1
2
Pin Name and Description
Active Low Reset.
Includes a 100kΩ pull - up resistor
Control Pin for SYNC I/O and DATA I/O.
Includes a 100kΩ pull - down resistor.
When low or not connected, internal SYNC and DATA are used, pins 9 and 10 are
outputs. When high, supply SYNC and DATA from an external source, pins 9 and
10 are inputs.
Black level capacitor.
White level capacitor.
Input for composite video signal with negative going syncs
Ground 0 volts.
Time constant resistor.
Controlling discharge rate of black and white level
capacitor voltages.
Address select for I
2
C bus.
[0010 0001] with AS set high, or [0010 0011] with AS
set low. Includes 100kΩ pull - down resistor.
Data input/output.
Sync input/output.
I
2
C bus serial clock.
Positive supply voltage +5V
±
10%
I
2
C bus bi-directional data port.
Active low open drain output data available signal to microprocessor.
Includes 100kΩ pull - up resistor
Crystal out,
27.75MHz fundamental crystal with on-chip 1MΩ resistor to XTI.
Crystal input.
BLC
WLC
VIDEO
GND
TCR
AS
DATA I/O
SYNC I/O
SCL
VDD
SDA
DAV
XTO
XTI
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3
微控制器 MCU
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