P ro du c t Br ie f
RTAX-DSP Radiation-Tolerant FPGAs
Radiation Performance
•
SEU-Hardened Registers Eliminate the Need for Triple-
Module Redundancy (TMR)
– Immune to Single-Event Upsets (SEU) to LET
TH
> 37
MeV-cm
2
/mg
– SEU Rate < 10
-10
Errors/Bit-Day in Worst-Case
Geosynchronous Orbit
Expected SRAM Upset Rate of <10
-10
Errors/Bit-Day with
Use of Error Detection and Correction (EDAC) IP
(included) with Integrated SRAM Scrubber
– Single-Bit Correction, Double-Bit Detection
– Variable-Rate Background Refreshing
Total Ionizing Dose Up to 300 krad (Si, Functional)
Single-Event Latch-Up Immunity (SEL) to LET
TH
> 117
MeV-cm
2
/mg
TM1019 Test Data Available
Leading-Edge Performance
•
•
•
•
High-Performance Embedded FIFOs
350+ MHz System Performance
500+ MHz Internal Performance
700 Mbps LVDS Capable I/Os
•
Specifications
•
•
•
•
•
Up to 4 Million Equivalent System Gates or 500 k
Equivalent ASIC Gates
Up to 16,800 SEU-Hardened Flip-Flops
Up to 840 I/Os
Up to 540 kbits Embedded SRAM
Manufactured on Advanced 0.15
µ
m CMOS Antifuse
Process Technology, 7 Layers of Metal
•
•
•
Features
•
•
•
Single-Chip, Nonvolatile Solution
1.5 V Core Voltage for Low Power
Flexible, Multi-Standard I/Os:
– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation
– Bank-Selectable I/Os – 8 Banks per Chip
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI
– JTAG Boundary Scan Testing (as per IEEE 1149.1)
– Differential I/O Standards: LVPECL and LVDS
– Voltage-Referenced I/O Standards: GTL+, HSTL
Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
– Hot-Swap Compliant with Cold-Sparing Support
(Except PCI)
Embedded Memory with Variable Aspect Ratio and
Organizations:
– Independent, Width-Configurable Read and Write
Ports
– Programmable Embedded FIFO Control Logic
– ROM Emulation Capability
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
Embedded Multiply/Accumulate
Blocks
•
•
•
•
Up to 120 Multiply/Accumulate Blocks
Fully SEU- and SET-Hardened
125 MHz Performance throughout Military Temperature
Range
Flexible, Cascadable Accumulate Function
Processing Flows
•
•
•
B-Flow – MIL-STD-883B
E-Flow – Actel Extended Flow
EV-Flow – Class V Equivalent Flow Processing
•
Prototyping Options
•
RTAX-DSP PROTO Devices with Same Functional and
Timing Characteristics as Flight Unit in a Non-Hermetic
Package
•
•
Table 1 •
RTAX-DSP Family Product Profile
RTAX2000D
2,000,000
250,000
8,960
17,920
17,920
64
64
288 k
4
4
8
684
2,052
1152
RTAX4000D
4,000,000
500,000
16,800
33,600
33,600
120
120
540 k
4
4
8
840
2,520
1272
Device
Capacity
Equivalent System Gates
ASIC Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Flip-Flops (maximum)
Embedded Multiply / Accumulate Blocks
DSP Mathblocks
Embedded RAM/FIFO (without EDAC)
Core RAM Blocks
Core RAM Bits (k = 1,024)
Clocks (segmentable)
Hardwired
Routed
I/Os
I/O Banks
User I/Os (maximum)
I/O Registers
Package
CCGA/LGA
S ep t e m b e r 2 0 0 8
© 2008 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
RTAX-DSP Radiation-Tolerant FPGAs
Ordering Information
RTAX2000D
_
CG
1152
B
Application
B = MIL-STD-883
Class
B
E = E-Flow (Actel
Space-Level
Flow)
EV =
Class
V Equivalent Flow Processing
Package Lead
Count
Package Type
CG
=
Ceramic Column Grid
Array
LG = Land
Grid
Array
Speed Grade
Blank =
Standard Speed
Part Number
RTAX2000D = 2,000,000 Equivalent
System Gates
RTAX4000D = 4,000,000 Equivalent
System Gates
Temperature Grade Offerings
Package
CG1152/LG1152
CG1272/LG1272
RTAX2000D
B, E, EV
–
RTAX4000D
–
B, E, EV
Note:
*The CCGA offerings (1152 and 1272) are offered with Six Sigma columns.
B = MIL-STD-883 Class B
E = E-Flow (Actel Space-Level Flow)
EV = Actel "V" Equivalent Flow
Speed Grade and Temperature Grade Matrix
Std.
B
E
EV
✓
✓
✓
Contact your local Actel representative for device availability.
Device Resources
Device
CG484/LG1152
CG896/LG1272
User I/Os (including clock buffers)
RTAX2000D
RTAX4000D
684
–
–
840
Note:
CCGA = Ceramic Column Grid Array, LGA = Land Grid Array
ii
P ro du ct B ri e f
RTAX-DSP Radiation-Tolerant FPGAs
Actel MIL-STD-883 Class B Product Flow
Table 2 •
Step
1
2
3
4
5
6
7
8
9
10
11
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Seal (Fine & Gross Leak Test)
Pre-Burn-In Electrical Parameters
Dynamic Burn-In
Interim (Post-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
a. Static Tests
(1) 25°C
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
(2) –55°C and +125°C
c. Switching Tests at 25°C
12
External Visual
1010, Condition C, 10 cycles minimum
2001, Y1 Orientation Only
Condition TBD
2020, Condition A
1014
In accordance
specification
with
applicable
Actel
device
Actel MIL-STD-883 Class B Product Flow for RTAX-DSP*
Screen
2010, Condition B
Method
Requirement
100%
100%
100%
100%
100%
100%
100%
100%
100%
All Lots
device
100%
1015, Condition D,
160 hours at 125°C or 80 hours at 150°C minimum
In accordance
specification
5%
In accordance with applicable Actel
specification, which includes a, b, and c:
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
with
applicable
Actel
device
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
5005, Table 1, Subgroup 9
2009
100%
Note:
*For CCGA devices, all Assembly, Screening, and TCI testing is performed at LGA level. Only QA electrical and mechanical visual
tests are performed after solder column attachment.
P rod u c t B ri ef
iii
RTAX-DSP Radiation-Tolerant FPGAs
Actel Extended Flow
Table 3 •
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Actel Extended Flow for RTAX-DSP
1, 2, 3
Screen
Destructive Bond Pull
4
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Radiographic (X-Ray)
Pre-Burn-In Electrical Parameters
Dynamic Burn-In
1010, Condition C, 10 cycles minimum
2001, Y1 Orientation Only
Condition TBD
2020, Condition A
2012, One View (Y1 Orientation) Only
In accordance with applicable Actel device specification
1015, Condition D,
240 hours at 125°C or 120 hours at 150°C minimum
1015, Condition C, 72 hours at 150°C or 144 hours at
125°C minimum
In accordance with applicable Actel device specification
5% Overall, 3% Functional Parameters at 25°C
In accordance with applicable Actel
specification, which includes a, b, and c:
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
device
100%
100%
100%
100%
All Lots
100%
100%
100%
2011, Condition D
2010, Condition A
Method
Requirement
Extended
Sample
100%
100%
100%
Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance with applicable Actel device specification
Static Burn-In
Interim (Post-Static-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
4
a. Static Tests
(1) 25°C
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
(2) –55°C and +125°C
c. Switching Tests at 25°C
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
5005, Table 1, Subgroup 9
1014
2009
100%
100%
15
16
Notes:
Seal (Fine & Gross Leak Test)
External Visual
1. Actel offers Extended Flow for users requiring additional screening beyond MIL-STD-833, Class B requirement. Extended Flow
incorporates the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S.
2. The Quality Conformance Inspection (QCI) for Extended Flow devices still complies to the MIL-STD-833, Class B requirement.
3. For CCGA devices, all Assembly/Screening/TCI testing is performed at LGA level. Only QA electrical and mechanical visual tests are
performed after solder column attachment.
4. Requirement for 100% nondestructive bond pull per Method 2003 is substituted by an extensive destructive bond pull to Method
2011 Condition D on an extended sample basis.
iv
P ro du ct B ri e f
RTAX-DSP Radiation-Tolerant FPGAs
Actel "EV" Flow (Class V Flow Equivalent Processing)
Table 4 •
Step
1
2
3
4
5
6
7
8
9
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
Particle Impact Noise Detection
Radiographic (X-Ray)
Pre-Burn-In Electrical Parameters
Dynamic Burn-In
1010, Condition C, 50 cycles minimum
2001, Y1 Orientation Only
Condition TBD
2020, Condition A
2012, One View (Y1 Orientation) Only
In accordance
specification
with
applicable
Actel
device
Actel "EV" Flow (Class V Equivalent Flow Processing) for RTAX-DSP
1, 2
Screen
Destructive Bond Pull
3
2011, Condition D
2010, Condition A
Method
Requirement
Extended Sample
100%
100%
100%
100%
100%
100%
100%
100%
1015, Condition D,
240 hours at 125°C or 120 hours at 150°C
minimum
with
applicable
Actel
device
10
11
12
13
14
Interim (Post-Dynamic-Burn-In) Electrical Parameters In accordance
specification
Static Burn-In
Interim (Post-Static-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
3, 4
a. Static Tests
(1) 25°C
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
(2) –55°C and +125°C
c. Switching Tests at 25°C
100%
100%
100%
All Lots
100%
1015, Condition C, 72 hours at 150°C or 144 hours
at 125°C minimum
In accordance
specification
with
applicable
Actel
device
5% Overall, 3% Functional Parameters at 25°C
In accordance with applicable Actel
specification, which includes a, b, and c:
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
device
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
5005, Table 1, Subgroup 9
1014
2009
MIL-PRF-38535, Appendix B, sec. B.4.2.c
100%
100%
All Wafer Lots
15
16
17
Notes:
Seal (Fine & Gross Leak Test)
External Visual
Wafer Lot Specific Life Test (Group C)
1. Actel offers "EV" flow for users requiring full compliance to the MIL-PRF-38535 Class V requirement.
The "EV" process flow is expanded from the existing E-flow requirement (it still meets the full SMD requirement for current E-flow
devices) with the intention to be in full compliance to the MIL-PRF-38535 Table IA and Appendix B requirement, but without the
official Class V certification from DSCC.
2. For CCGA devices, all Assembly/Screening/TCI testing is performed at LGA level. Only QA electrical and mechanical visual tests are
performed after solder column attachment.
3. The requirement for 100% nondestructive bond pull per Method 2003 is fulfilled by substitution of an extensive extended sample
basis.
4. Read and record performed at –55°C and +125°C (no delta calculation).
P rod u c t B ri ef
v
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
