THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
MV1444
PRELIMINARY INFORMATION
DS3108 2.2
MV1444
COMBINED PCM TIMESLOT ZERO TRANSMITTER
AND HDB3 ENCODER
The MV1444 combines the Timeslot Zero Transmitter and
HDB3 Encoder functions required by a 2.048Mbit 30 channel
PCM transmission link operating in accordance with the
appropriate CCITT Recommendations and forms part of the
GPS 2Mbit PCM signalling series of devices. The circuit is
fabricated in CMOS and operates from a single +5V supply
with all inputs and outputs being TTL compatible.
The Timeslot Zero Transmitter half of the circuit is
responsible for generating the timeslot zero synchronising
word of a 2Mbit PCM link in accordance with CCITT
Recommendation G.704. This function is performed by
alternately generating sync frames, containing the CCITT
Frame Alignment Signal, and non-sync frames containing user
data bits.
The data being output from the Timeslot Zero Transmitter
is multiplexed together with data for the remaining 31 timeslots
by the transmission multiplexer and the PCM data stream thus
created is fed in to the HDB3 Encoder.
The HDB3 Encoder half of the circuit is responsible for
converting the incoming PCM data stream from the
transmission multiplexer from NRZ form in to pseudo-ternary
HDB3 transmission code for transmission over a 2Mbit PCM
link. This process is carried out in accordance with Annex A to
CCITT Recommendation G. 703 and ensures adequate clock
recovery at the PCM receiver.
D
CLK
TXD1
TXD2
D1S
D1N
TZS
STM
GND2
1
2
3
4
5
6
7
8
9
18
17
16
VDD
FRS
Q-TMUX
D8N
D7N
D6N
D5N
D4N
D3N
MV
1444
14
13
12
11
10
15
DG18, DP18
Q-TMUX
NC
NC
NC
D8N
D7N
D6N
D5N
24
23
22
21
20
19
12 13 14 15 16 17 18
GND1
TXD1
VDD
NC
4
TXD2
NC
NC
D1S
5
6
7
8
9
10
11
3
2
1
28 27 26
25
FEATURES
s
Single +5V supply.
s
All Inputs and Outputs TTL compatible.
s
Timeslot Zero Transmitter generates Frame Alignment
Signal in accordance with CCITT Recommendation G.704.
s
Enables access to 6 User data bits and 2 International data
bits of Timeslot Zero.
s
On-chip Transmission Multiplexer allows combination of
Timeslot Zero data with remaining 31 Timeslots of data.
s
HDB3 Encoding carried out in Accordance with Annex A to
CCITT Recommendation G.703.
MV
1444
D1N
NC
NC
NC
D3N
FRS
CLK
D
STM
GND2
D4N
TZS
HG28, HP28
Fig. 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are limiting values above
which operating life may be shortened or specified parameters
may be degraded.
ORDERING INFORMATION
MV1444/IG/DGAS
MV1444/IG/DPAS
MV1444/IG/HGAS
MV1444/IG/HPAS
ELECTRICAL RATINGS
Supply Voltage
Input Voltage
Output Voltage
-0.5V to +7V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
1
MV1444
D8N
D6N
D7N
D5N
D4N
D3N
TZS
D
Transmission
Multiplexer
D1S
Timeslot Zero
Transmitter
TS0 PCM Data
Q-TMUX
D1N
FRS
CLK
HDB3
Encoder
TXD1
TXD2
FUNCTIONAL DESCRIPTION
The MV1444 combines the Timeslot Zero Transmitter,
Transmission Multiplexer and HDB3 Encoder functions
required by a 2.048Mbit 30 channel PCM transmission link
operating in accordance with the appropriate CCITT
Recommendations. The block diagram of the MV1444 is
shown in Fig. 2, and the function of each block is now
described separately.
Timeslot Zero Transmitter
The Timeslot Zero Transmitter circuit generates the
timeslot zero synchronising word required by a 2.048Mbit PCM
link in accordance with CCITT Recommendation G.704.
During alternate frames, denoted sync frames, the CCITT
Frame Alignment Signal (FAS - 0011011) is combined with the
International / CRC data bit input, D1S, for bit 1 and injected in
to the transmission multiplexer for HDB3 Encoding. During the
other interleaved frames, denoted non-sync frames, bit 2 of
timeslot zero is set to ‘1’ to avoid imitation of the FAS and this
is combined with the second International / CRC data bit, D1N,
for bit 1 and the user data bits, D3N-D8N, for bits 3 to 8, and
again output to the transmission multiplexer.
In order to perform this function the Timeslot Zero
Transmitter requires 2 timing inputs in addition to the parallel
data bit inputs, pins CLK and FRS. The CLK input is a
2.048MHz clock input whilst FRS is a high going pulse, 8 clock
periods long, which is required to mask timeslot zero of each
frame. In addition to the PCM data stream output the Timeslot
Zero Transmitter produces a timing output, TZS, which
changes state one clock period after the end of Timeslot Zero
and is high during the transmission of timeslot zero of sync
frames. The timing diagram of the entire MV1444 is shown in
Fig.3.
VDD
GND1
GND2
STM
Fig. 2 Block diagram
Transmission Multiplexer
The Transmission Multiplexer circuit mutiplexes together
the output from the Timeslot Zero Transmitter with the PCM
data stream for the remaining 31 timeslots being input on the D
pin. This multiplexing is carried out under control of the FRS
input such that the output from the Timeslot Zero Transmitter is
selected whenever FRS is high. The output from the
transmission multiplexer is input to the HDB3 Encoder and is
also available as a device output on the Q-TMUX pin.
HDB3 Encoder
The HDB3 Encoder is responsible for converting the NRZ
data being output by the transmission multiplexer into pseudo-
ternary form for transmission over a 2.048Mbit PCM link. This
conversion is carried out in accordance with the HDB3 coding
laws specified in CCITT Recommendation G.703, Annex A.
High Density Bipolar 3 (HDB3) is a ternary transmission
code in which the number of consecutive zeros which may
occur is restricted to three, to ensure adequate clock recovery
at the receiver. In any sequence of four consecutive binary
zeroes, the last zero is substituted by a mark of the same
polarity of the previous mark, thus breaking the Alternate Mark
Inversion (AMI) code. This mark is termed a violation. In
addition, the first zero may also be substituted by a mark if the
last mark and last violation are of the same polarity. This mark
does not violate the AMI code and ensures that successive
violations alternate in polarity and as such introduce no DC
component to the HDB3 signal. The data to be encoded is the
PCM data stream being output by the transmission multiplexer
and this is latched into the HDB3 Encoder by the falling edge of
CLK. The HDB3 Encoder has two outputs, TXD1 and TXD2,
which represent the HDB3 encoded PCM data stream in
pseudo-ternary form. If a mark or violation is to be transmitted
the output pulses high after the rising edge of clock, with the
length of the pulse set by the clock high pulse width.
2
MV1444
CLK
FRS
D1S
TZS
TS0
OUTPUT
D
d1s
d1s
Q-TMUX
d1s
B
B
B
TXD1
4.5 Clock Periods
B
B
B
TXD2
Timeslot Zero Transmitter Transmitting Sync Word
CLK
FRS
D1N
D3N-
D8N
d1n
d3n-d8n
TZS
TS0
OUTPUT
D
d1n
d3n
d4n
d5n
d6n
d7n
d8n
Q-TMUX
d1n
d3n
d4n
d5n
d6n
d7n
d8n
B
B
V
TXD1
B
B
TXD2
Timeslot Zero Transmitter Transmitting Non-sync Word
NOTES
1) The encoded HDB3 outputs, TXD1/2 are delayed by 4.5 clock periods with respect to Q-TMUX.
2) B is a mark, V is a HDB3 violation.
3) The TXD outputs are produced under the assumption that d1s=d1n=1, d3n-d8n=0.
4) Both diagrams assume the last mark and last violation occured on TXD2.
Fig. 3 MV1444 Timing diagrams
3
MV1444
PIN DESCRIPTIONS
Pin name
Pin no.
DG18
-
1
Pin description
HG28
1
2
Digital Ground. OV (Note 1)
2.048Mbit PCM Voice Channel Input to Transmission Multiplexer. Data on this pin is input
to the transmission multiplexer during timeslots 1-31 of a CCITT PCM frame for HDB3
encoding. After multiplexing this data is latched in to the HDB3 Encoder by the
falling edge of CLK.
2.048MHz System Clock Input to Timeslot Zero Transmitter and HDB3 Encoder.
HDB3 Encoded Pseudo-Ternary Output 1 from HDB3 Encoder. The PCM data stream
produced by the transmission multiplexer is HDB3 encoded and output on this pin and pin
TXD2. This output is always low during the low half cycle of clock and is only high during
the high half cycle of clock if a mark is to be output. There is a 4.5 clock period delay from
the falling edge of CLK to TXD1.
HDB3 Encoded Pseudo-Ternary Output 2 from HDB3 Encoder. See Pin TXD1 description.
International / CRC Data Bit Input to Timeslot ZeroTransmitter for Sync Frames. The data
on this pin is output to the transmission multiplexer during bit 1, timeslot zero of sync
frames and must be set up prior to the rising edge of FRS during sync frames.
International / CRC Data Bit Input to Timeslot Zero Transmitter for Non-Sync Frames.
The data on this pin is output to the transmission multiplexer during bit 1, timeslot zero of
non-sync frames and must be set up prior to the rising edge of FRS during non-sync
frames.
Timeslot Zero Sync Frame Output from Timeslot Zero Transmitter. This 4KHz output
changes state at the end of bit 1, timeslot 1 ( Note 2) of every frame and is high during
timeslot zero of sync frames.
Scan Path Test Global Mode Pin. A logic high on this pin configures the MV1444 in scan
test mode. For normal operation this pin should be tied low.
Digital Ground. OV (Note 1)
GND1
D
CLK
TXD1
2
3
3
4
TXD2
D1S
4
5
5
8
D1N
6
9
TZS
7
13
STM
8
14
GND2
9
15
4
测试/测量
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