CoreCORDIC CORDIC RTL Generator
Product Summary
Intended Use
•
COordinate Rotation DIgital Computer (CORDIC)
Rotator Function for Actel FPGAs
•
Evaluation Version
–
Supports CORDIC Engine and Test Harness
Generation with Limited Parameters. Fully
Supported in Libero IDE.
Synthesis and Simulation Support
•
•
•
Libero IDE
Synthesis:
Synplicity
®
,
Synopsys
®
Compiler/FPGA Compiler), Exemplar™
(Design
Key Features
•
•
•
•
•
•
•
•
•
•
Vector Rotation – Conversion of Polar Coordinates
to Rectangular Coordinates
Vector Translation – Conversion of Rectangular
Coordinates to Polar Coordinates
Sine and Cosine Calculation
Vector (X,
Y)
Magnitude
(arctan[X/Y]) Calculation
X
+
Y
2
2
Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators.
Table of Contents
General Description ................................................... 1
CoreCORDIC Device Requirements ........................... 4
Architectures .............................................................. 5
I/O Formats ................................................................. 7
CoreCORDIC Configuration Parameters ................... 9
I/O Signal Description ................................................ 9
I/O Interface and Timing .......................................... 11
References ................................................................ 12
A Sample Configuration File ................................... 13
Ordering Information .............................................. 13
Datasheet Categories ............................................... 13
Appendix I ................................................................ 14
Appendix II ............................................................... 15
and Phase
8-Bit to 48-Bit Configurable Word Size
8 to 48 Configurable Number of Iterations
Parallel Pipelined Architecture for the Fastest
Calculation
Bit-Serial Architecture for the Smallest Area
Word-Serial Architecture for Moderate Speed and
Area
Word Parallel Data I/Os
Supported Families
•
•
•
•
•
•
•
Fusion
ProASIC
®
3/E
ProASIC
PLUS ®
Axcelerator
®
RTAX-S
SX-A
RTSX-S
General Description
CoreCORDIC is an RTL generator that produces an Actel
FPGA–optimized CORDIC engine. The CORDIC algorithm
by J. Volder provides an iterative method of performing
vector rotations using shifts and adds only. The articles
listed in
"References" on page 12
present a detailed
description of the algorithm.
Depending on the configuration defined by the user, the
resulting module implements pipelined parallel, word-
serial, or bit-serial architecture in one of two major
modes: rotation or vectoring. In rotation mode, the
CORDIC rotates a vector by a specified angle. This mode
is used to convert polar coordinates to Cartesian
Core Deliverables
•
Full Version
–
CoreCORDIC RTL Generator. Generates User-
Defined CORDIC Model and Test Harness. Fully
Supported in the Actel Libero
®
Integrated
Design Environment (IDE)
March 2006
© 2006 Actel Corporation
v 2 .0
1
CoreCORDIC CORDIC RTL Generator
coordinates, for general vector rotation, and also to
calculate sine and cosine functions (see
Figure 1).
"Appendix I" on page 14
presents mathematical
coordinate conversion formulae, and
"Appendix II" on
page 15
describes examples of a few of the most used
CORDIC modes.
Magnitude r
Phase
θ
CORDIC
Engine
x
y
The gain can be compensated for elsewhere in many
applications when the system includes the CORDIC
engine. To assist a user in doing so, the CoreCORDIC
software computes the precise value of the gain and
displays it on a screen. In the cases when only relative
magnitude is of importance—for example, spectrum
analysis and AM demodulation—the constant gain can
be neglected. When calculating sine/cosine, the CORDIC
gets initialized with a constant reciprocal value of the
processing gain
r
= 1/K.
EQ 1
and
EQ 2
become
X
=
cos
θ
Y
=
sin
θ
Figure 1 •
CORDIC Engine in Rotation Mode
In vectoring mode, the CORDIC rotates the input vector
towards the
x
axis while accumulating a rotation angle.
Vectoring mode is used to convert Cartesian vector
coordinates to polar coordinates; i.e., to calculate the
magnitude and phase of the input vector (Figure
2).
Thus, the gain does not impact the sine/cosine results or
the phase output.
To perform the conversions, the CORDIC processor
implements the iterative CORDIC equations
EQ 5
through
EQ 7.
x
i
+
1
=
x
i
–
y
i
×
d
i
×
2
–
i
x
y
CORDIC
Engine
Magnitude r
Phase
EQ 5
y
i
+
1
=
y
i
+
x
i
×
d
i
×
2
–
i
θ
EQ 6
a
i
+
1
=
a
i
–
d
i
×
arctan
(
2
)
EQ 7
–
i
Figure 2 •
CORDIC Engine in Vectoring Mode
The CORDIC results, such as
x, y,
and
r,
are scaled by the
inherent processing gain,
K,
which depends on number
of iterations and converges to about 1.647 after a few
iterations. The gain is constant for a given number of
iterations. When performing Cartesian/polar coordinate
conversion, the CORDIC computes the results shown in
EQ 1
and
EQ 2
in rotation mode.
X
=
K
⋅
r
⋅
cos
xθ
EQ 1
Y
=
K
⋅
r
⋅
sin
θ
EQ 2
The sign-controlling function
d
i
takes the values shown
in
EQ 8
and
EQ 9:
•
In rotation mode
d
i
= –1 if a
i
< 0, otherwise d
i
= 1
EQ 8
•
In vectoring mode
d
i
= 1 if y
i
< 0, otherwise d
i
= –1
EQ 9
EQ 3
and
EQ 4
show the CORDIC results in vectoring
mode.
r
=
K
⋅
X
+
Y
2
2
EQ 3
θ
=
arctan
(
Y
⁄
X
)
EQ 4
The input and output data is represented as n-bit words,
where n is a user-defined number in the range from 8 to
48. The number of iterations is also defined by a user in
the same range. The CORDIC result accuracy improves
when the number of iterations is increased, as long as
the number of iterations does not exceed data bit width.
In other words, the bit width limits the number of
meaningful iterations.
A system that utilizes the CORDIC engine (Figure
3 on page 3)
consists of the following:
•
•
•
A data source generating the vector data to be converted by the CORDIC
The CORDIC module configured to work in either rotation or vectoring mode
A data receiver accepting the newly converted vector data
2
v2.0
CoreCORDIC CORDIC RTL Generator
Master Clock
clkEn
x0
y0
Data
Source
a0
ldData
rst
Global Reset
nGrst
CORDIC
Engine
xn
yn
an
OR
rdyOut
Data
Receiver
Figure 3 •
CORDIC-Based System
The negative
nGrst
signal resets the CORDIC engine and, optionally, the entire system. After the reset (input
nGrst
taken high), the CORDIC module is ready to receive data samples to be processed. The module synchronous reset input
rst
can be used to bring the CORDIC unit to the ready state at any time after the initial global reset.
Note: The CORDIC module will lose half-processed data when
rst
is taken high by the system.
The data source supplies the CORDIC engine with the data to be converted. Depending on the mode (rotation or
vectoring), the system uses different CORDIC inputs and outputs to enter and obtain the data.
Table 1
shows the input/
output signals used in each mode.
Table 1 •
CORDIC Connection to the System
Input Data
CORDIC Input
Common Rotation Modes
Input vector magnitude
Constant 0
Input vector phase
x0
y0
a0
Output vector coordinate X
Output vector coordinate Y
N/A
sin(
θ
)
cos(
θ
)
N/A
xn
yn
an
Output Data
CORDIC Output
Rotation Mode: Sine/Cosine Table Generator
Constant reciprocal value of the processing gain r = 1/K
Constant 0
Sine/cosine argument
θ
x0
y0
a0
Vectoring Mode
Input vector coordinate X
Input vector coordinate Y
Constant 0
x0
y0
a0
Output vector magnitude r
N/A
Output vector phase
θ
xn
yn
an
xn
yn
an
The system accompanies every new pair of the input data samples with the one-bit
ldData
signal. Upon receiving the
ldData
bit, the module assumes the vector coordinates are present on input data busses. Once the CORDIC results are
ready, the engine puts these out, accompanied by the one-bit
rdyOut
signal. Upon receiving the
rdyOut
bit, the system
can supply a new pair of input data and generate another
ldData
signal.
CoreCORDIC can generate three different CORDIC core implementation architectures and an appropriate testbench:
•
•
•
Parallel pipelined
Word-serial
Bit-serial
The parallel pipelined architecture provides the fastest speed, whereas the bit-serial architecture provides the smallest
area. The word-serial architecture provides the trade-off of moderate speed and area.
v2.0
3
CoreCORDIC CORDIC RTL Generator
CoreCORDIC Device Requirements
Table 2
provides typical utilization and performance data for CoreCORDIC, implemented in various Actel devices with
the CORDIC engine bit resolution set to 24 bits and the number of iterations set to 24. Device utilization and
performance will vary depending upon the architecture chosen and the configuration parameters used. Time-driven
settings were used when synthesizing parallel architectures; area optimization settings were used in other cases.
The CORDIC core does not utilize on-chip RAM blocks.
Table 2 •
CoreCORDIC Device Utilization and Performance
Cells or Tiles
Device
Fusion
AFS600
AFS600
AFS600
ProASIC3/E
A3P250
A3P250
A3P1000
ProASIC
PLUS
APA150
APA150
APA1000
Axcelerator
AX125
AX125
AX500
RTAX-S
RTAX250S
RTAX250S
RTAX1000S
Bit-serial
Word-serial
Parallel
Rotate
Vector
Rotate
Vector
Rotate
Vector
196
185
413
405
4,633
4,617
Bit-serial
Word-serial
Parallel
Rotate
Vector
Rotate
Vector
Rotate
Vector
196
185
413
405
4,633
4,617
Bit-serial
Word-serial
Parallel
Rotate
Vector
Rotate
Vector
Rotate
Vector
393
394
824
822
14,301
16,594
Bit-serial
Word-serial
Parallel
Rotate
Vector
Rotate
Vector
Rotate
Vector
297
296
664
658
12,541
14,832
Bit-serial
Word- serial
Parallel
Rotate
Vector
Rotate
Vector
Rotate
297
293
668
660
11,810
Engine
Architecture
Mode
Comb
Seq
Speed Grade –2
110
108
103
101
1,884
Speed Grade –2
110
108
103
101
1,906
1,981
108
107
114
114
1,889
1,936
Speed Grade –2
106
105
124
133
1,832
1,835
Speed Grade –1
106
105
124
133
1,832
1,835
302
290
537
538
6,465
6,452
8%
7%
14%
14%
36%
36%
92
100
74
75
89
81
6,283
5,780
338
333
11.2
12.3
302
290
537
538
6,465
6,452
15%
14%
27%
27%
80%
80%
113
115
103
109
130
124
5,115
5,026
243
229
7.7
8.1
407
404
767
759
14,447
16,813
501
501
938
936
16,190
18,530
7%
7%
12%
12%
59%
68%
8%
8%
15%
15%
29%
33%
83
93
30
26
46
62
61
63
20
19
32
37
6,964
6,215
833
962
21.7
16.1
9,475
9,175
1,250
1,316
31.3
27.0
407
401
771
761
13,694
3%
3%
6%
6%
99%
88
87
30
27
46
6,568
6644
833
926
21.7
Total
Utilization Clock Rate,
%
MHz
Transform
Time,
nsec
Speed Grade STD
Note:
The above data were obtained by typical synthesis and place-and-route methods. Other core parameter settings can result in
different utilization and performance values.
4
v2.0
CoreCORDIC CORDIC RTL Generator
Table 2 •
CoreCORDIC Device Utilization and Performance (Continued)
Cells or Tiles
Device
54SX-A
54SX72A
54SX72A
RT54SX-S
RT54SX72S
RT54SX72S
Bit-serial
Word-serial
Rotate
Vector
Rotate
Vector
189
190
677
664
Bit-serial
Word-serial
Rotate
Vector
Rotate
Vector
190
195
656
643
Engine
Architecture
Mode
Comb
Seq
Speed Grade –2
105
105
132
124
Speed Grade –1
104
104
132
125
293
294
809
789
5%
5%
13%
13%
55
55
33
34
10,509
10,509
758
735
295
300
788
767
5%
5%
13%
13%
67
71
55
50
8,627
8,141
455
500
Total
Utilization Clock Rate,
%
MHz
Transform
Time,
nsec
Note:
The above data were obtained by typical synthesis and place-and-route methods. Other core parameter settings can result in
different utilization and performance values.
Architectures
Word-Serial Architecture
Direct implementation of the CORDIC iterative equations (see
"References" on page 12)
yields the block diagram
shown in
Figure 4.
The vector coordinates to be converted, or initial values, are loaded via multiplexers into registers
RegX, RegY, and RegA. RegA, along with an adjacent adder/subtractor, multiplexer, and a small arctan LUT, is often
called an angle accumulator. Then on each of the following clock cycles, the registered values are passed through
adders/subtractors and shifters. The results described by
EQ 5
through
EQ 7 on page 2
are loaded back to the same
registers. Every iteration takes one clock cycle, so that in
n
clock cycles,
n
iterations are performed and the converted
coordinates are stored in the registers.
x
0
+/–
>> i
d
i
>> i
y
0
d
i
–/+
arctan
LUT
a
0
+/–
RegX
Sign
y
i
x
n
Mode: Rotation/Vectoring
Figure 4 •
Word-Serial CORDIC Block Diagram
RegY
Sign
a
i
y
n
Sign Controlling Logic
RegA
a
n
d
i
v2.0
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