Core8051
Product Summary
Intended Use
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Embedded System Control
Communication System Control
I/O Control
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– Wait Cycles to Access Fast/Slow ROM
– Dual Data Pointer to Fast Data Block Transfer
Special Function Register (SFR) Interface
– Services up to 101 External SFRs
Optional On-Chip Instrumentation (OCI) Debug
Logic
Supports all Major Actel Device Families
Optional Power-Saving Modes
Key Features
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100% ASM51 (8051/80C31/80C51) Compatible
Instruction Set
1
Control Unit
– 8-Bit Instruction Decoder
– Reduced Instruction Time of up to 12 Cycles
Arithmetic Logic Unit
– 8-Bit Arithmetic and Logical Operations
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Boolean Manipulations
8 by 8-Bit Multiplication and 8 by 8-Bit Division
Supported Families
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Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
SX-A
RTSX-S
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32-Bit I/O Ports
– Four 8-Bit I/O Ports
– Alternate Port Functions, such as External
Interrupts, Provide Extra Port Pins when
Compared with the Standard 8051
Serial Port
– Simultaneous Transmit and Receive
– Synchronous Mode, Fixed Baud Rate
– 8-Bit UART Mode, Variable Baud Rate
– 9-Bit UART Mode, Fixed Baud Rate
– 9-Bit UART Mode, Variable Baud Rate
– Multiprocessor Communication
Two 16-Bit Timer/Counters
Interrupt Controller
– Four Priority Levels with 13 Interrupt Sources
Internal Data Memory Interface
– Can Address up to 256B of Data Memory Space
External Memory Interface
– Can Address up to 64kB of External Program
Memory
– Can Address up to 64kB of External Data
Memory
– Demultiplexed Address/Data Bus Enables Easy
Connection to Memory
– Variable Length MOVX to Access Fast/Slow
RAM or Peripherals
Core Deliverables
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Evaluation Version
– Compiled RTL Simulation Model Fully Supported in
the Actel Libero
®
Integrated Design Environment
(IDE)
Netlist Version
– Structural Verilog and VHDL Netlists (with and
without I/O Pads) Compatible with the Actel
Designer Software Place-and-Route Tool
– Compiled RTL Simulation Model Fully
Supported in Actel Libero IDE
RTL Version
– Verilog and VHDL Core Source Code
– Core Synthesis Scripts
Testbench (Verilog and VHDL)
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Synthesis and Simulation Support
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Synthesis
– Synplicity
®
– Synopsys
®
(Design Compiler
TM
, FPGA Compiler
TM
,
FPGA Express
TM
)
– Exemplar
TM
Simulation
– OVI - Compliant Verilog Simulators
– Vital - Compliant VHDL Simulators
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1. For more information, see the Core8051 Instruction Set Details User’s Guide
December 2005
© 2005 Actel Corporation
v 6 .0
1
Core8051
Core Verification
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Comprehensive VHDL and Verilog Testbenches
Users Can Easily Add Custom Tests by Modifying
the User Testbench Using the Existing Format
MUL and DIV instructions. Furthermore, each cycle in the
8051 used two memory fetches. In many cases, the second
fetch was a "dummy" fetch and extra clocks were wasted.
Table 1
shows the speed advantage of Core8051 over the
standard 8051. A speed advantage of 12 in the first
column means that Core8051 performs the same
instruction 12 times faster than the standard 8051. The
second column in
Table 1
lists the number of types of
instructions that have the given speed advantage. The
third column lists the total number of instructions that
have the given speed advantage. The third column can be
thought of as a subcategory of the second column. For
example, there are two types of instructions that have a
three-time speed advantage over the classic 8051, for
which there are nine explicit instructions.
Table 1 •
Core8051 Speed Advantage Summary
Speed
Advantage
24
12
9.6
8
6
4.8
4
3
Average: 8.0
Number of
Instruction
Types
1
27
2
16
44
1
18
2
Sum: 111
Number of
Instructions
(Opcodes)
1
83
2
38
89
2
31
9
Sum: 255
Contents
General Description .................................................... 2
Core8051 Device Requirements ................................. 4
Core8051 Verification ................................................ 5
I/O Signal Descriptions ............................................... 5
Memory Organization ................................................ 8
Special Function Registers ........................................ 10
Instruction Set ........................................................... 11
Instruction Definitions ............................................. 19
Instruction Timing .................................................... 20
Core8051 Engine ...................................................... 27
Timers/Counters ........................................................ 28
Serial Interface .......................................................... 30
Interrupt Service Routine Unit ................................. 32
ISR Structure ............................................................. 35
Power Management Unit ........................................ 36
Power Management Implementation ..................... 36
Interface for On-Chip Instrumentation (Optional) . 37
Ordering Information .............................................. 39
List of Changes ......................................................... 40
Datasheet Categories ............................................... 40
General Description
The Core8051 macro is a high-performance, single-chip, 8-
bit microcontroller. It is a fully functional eight-bit
embedded controller that executes all ASM51 instructions
and has the same instruction set as the 80C31. Core8051
provides software and hardware interrupts, a serial port,
and two timers.
The Core8051 architecture eliminates redundant bus
states and implements parallel execution of fetch and
execution phases. Since a cycle is aligned with memory
fetch when possible, most of the one-byte instructions are
performed in a single cycle. Core8051 uses one clock per
cycle. This leads to an average performance improvement
rate of 8.0 (in terms of MIPS) with respect to the Intel
device working with the same clock frequency.
The original 8051 had a 12-clock architecture. A machine
cycle needed 12 clocks, and most instructions were either
one or two machine cycles. Therefore, the 8051 used
either 12 or 24 clocks for each instruction, except for the
The average speed advantage is 8.0. However, the real
speed improvement seen in any system will depend on the
instruction mix.
Core8051 consists of the following primary blocks:
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Memory Control Block – Logic that Controls
Program and Data Memory
Control Processor Block – Main Controller Logic
RAM and SFR Control Block
ALU – Arithmetic Logic Unit
Reset Control Block – Provides Reset Condition
Circuitry
Clock Control Block
Timer 0 and 1 Block
ISR – Interrupt Service Routine Block
Serial Port Block
Port Registers Block
PMU – Power Management Unit Block
OCI block – On-Chip Instrumentation Logic for
Debug Capabilities
2
v6.0
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