ARINC 429 Bus Interface
Product Summary
Intended Use
•
•
ARINC 429 Transmitter (Tx)
ARINC 429 Receiver (Rx)
•
•
–
Core Deliverables
•
Evaluation Version
–
Compiled RTL Simulation Model, Compliant
with the Actel Libero
®
Integrated Design
Environment (IDE)
Structural VHDL and Verilog Netlists
VHDL or Verilog Core Source Code
Synthesis Scripts
Netlist Version
RTL version
–
–
Key Features
•
•
•
•
Supports ARINC Specification 429-16
Configurable up to 16 Rx and 16 Tx Channels
Programmable FIFO Depth
–
–
–
•
–
–
•
•
•
•
Up to 512 Words
Rx and Tx Channels independently
Up to 64 Words
Programmable Interrupt Generation
•
•
Verification Testbench – Verilog
User Testbenches
–
–
Libero IDE Compatible
VHDL and Verilog
Configurable Label Memory Size
Rx and Tx Channels independently
Up to 256 Words
Development System
•
•
Complete ARINC 429 Rx/Tx
Implementation
–
–
•
Implemented in an APA600 Device
Controlled Via an External Terminal Using
Core8051 and RS232 Links
Internal, Wrap-Around Testing
Software Compatible with Legacy Devices
Selectable Clock Speed
–
–
–
1, 10, 16, or 20 MHz
12.5 100 kbps
Optional 50 kbps
Provides Direct CPU Access to Memory
Simple Interface to Core8051
EDAC Support with RTAX-S Family
Supports Standard Line Drivers and Receivers
•
Selectable Data Rate on Each Channel
Includes Line Driver and Receiver Components
Synthesis and Simulation Support
•
•
Directly Supported within the Actel Libero IDE
Synthesis:
–
–
–
–
–
Synplicity®
Exemplar
TM
Synopsys
®
Vital-Compliant VHDL Simulators
OVI-Compliant Verilog Simulators
•
CPU Interface
–
–
•
•
•
Memory
–
–
ARINC 429 Bus Interface
Available as Integrated Tx and Rx
Simulation
Supported Families
•
•
•
•
•
Fusion
ProASIC
®
3/E
ProASIC
PLUS®
Axcelerator
®
RTAX-S
Verification and Compliance
•
•
Actel-Developed Simulation Testbench
Core
Implemented
Development System
on
the
ARINC
429
September 2006
© 2006 Actel Corporation
v 5 .0
1
ARINC 429 Bus Interface
Contents
General Description .................................................... 2
ARINC 429 Overview .................................................. 2
Core429 Device Requirements ................................... 3
Memory Requirements ............................................... 4
Core429 Overview ...................................................... 5
Default Mode ............................................................. 5
Functional Description ............................................... 5
Legacy Mode ............................................................... 7
Core Parameters ......................................................... 8
I/O Signal Descriptions ............................................... 8
Default Mode Operation ......................................... 10
Legacy Operation ..................................................... 13
Status Register .......................................................... 15
CPU Interface Timing for Default Mode ................. 16
Clock Requirements .................................................. 17
Core429 Verification ................................................ 17
Testbench .................................................................. 17
Line Drivers ............................................................... 18
Line Receivers ........................................................... 18
Loopback Interface ................................................... 18
Development System ................................................ 18
Ordering Information .............................................. 19
List of Changes ......................................................... 20
Datasheet Categories ............................................... 21
Rx I/F
CPU
Glue
Logic
CPU
Interface
RxHi
RxLo
TxHi
TxLo
Tx I/F
CoreARINC429
Actel FPGA
Figure 1 •
Typical Core429 System—One Tx and One Rx
ARINC 429 Overview
ARINC 429 is a two-wire, point-to-point data bus that is
application-specific for commercial and transport
aircraft. The connection wires are twisted pairs. Words
are 32 bits in length and most messages consist of a
single data word. The specification defines the electrical
standard and data characteristics and protocols.
ARINC 429 uses a unidirectional data bus standard (Tx
and Rx are on separate ports) known as the Mark 33
Digital Information Transfer System (DITS). Messages are
transmitted at 12.5, 50 (optional), or 100 kbps to other
system elements that are monitoring the bus messages.
The transmitter is always transmitting either 32-bit data
words or the Null state.
The ARINC standard supports High, Low, and Null states
(Figure
2).
A minimum of four Null bits should be
transmitted between ARINC words. No more than 20
receivers can be connected to a single bus (wire pair) and
no less than one receiver, though there will normally be
more.
General Description
Core429 provides a complete Transmitter (Tx) and
Receiver (Rx). A typical system implementation using
Core429 is shown in
Figure 1.
The core consists of three main blocks: Transmit, Receive,
and CPU Interface (Figure
1).
Core429 requires
connection to an external CPU. The CPU interface
configures the transmit and receive control registers and
initializes the label memory. The core interfaces to the
ARINC 429 bus through an external ARINC 429 line driver
and line receiver. A detailed description of the Rx
interface and Tx interface is provided in the
"Functional
Description" section on page 5.
1
High +5
A Null 0
Low –5
High +5
B Null 0
Low –5
1
2
3
4
5
6
7
8
9 10
32 Bit
Number
"A" Leg
"B" Leg
0
1
1
0
1
0
1
0
0
1
Data
Figure 2 •
ARINC Standard
External Components
There are two external components required for proper
operation of Core429:
•
•
Standard ARINC 429 line driver
Standard ARINC 429 line receiver
Figure 3 on page 3
shows the bit positions of ARINC
data.
Each ARINC word contains five fields:
•
Parity
2
v5.0
ARINC 429 Bus Interface
•
•
•
•
Sign/Status Matrix
Data
Source/Destination Identifiers
Label
receiver the data is intended. Bits 1 to 8 contain a label
(label words) identifying the data type.
Label words are quite specific in ARINC 429. Each aircraft
may be equipped with different electronic equipment
and systems needing interconnection. A large amount of
equipment may be involved, depending on the aircraft.
The ARINC specification identifies the equipment ID, a
series of digital identification numbers. Examples of
equipment are Flight Management Computers, Inertial
Reference Systems, Fuel Tanks, Tire Pressure Monitoring
Systems, and GPS Sensors.
The parity bit is bit 32 (the MSB). SSM is the Sign/Status
Matrix and is included as bits 30 and 31. Bits 11 to 29
contain the data. Binary Coded Decimal (BCD) and binary
encoding (BNR) are common ARINC data formats. Data
formats can also be mixed. Bits 9 and 10 are Source/
Destination Identifiers (SDI) and indicate for which
32
P
31
SSM
30
29
DATA
MSB
PAD
11
DISCRETES
LSB
10
SDI
9
8
LABEL
1
Figure 3 •
ARINC Data Bit Positions
Transmission Order
The least significant bit of each byte, except the label, is transmitted first, and the label is transmitted ahead of the
data in each case. The order of the bits transmitted on the ARINC bus is as follows:
8, 7, 6, 5, 4, 3, 2, 1, 9, 10, 11, 12, 13 … 32.
Core429 Device Requirements
Core429 can be implemented in several Actel FPGA devices.
Table 1
through
Table 5 on page 4
provide typical
utilization figures using standard synthesis tools for different Core429 configurations.
Table 1
assumes that the label
size is set to 64 and FIFO depth is set to 64.
Table 1 •
Device Utilization for One Tx Module
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
Table 2 •
Combinatorial
363
363
441
212
258
Sequential
147
147
146
145
171
Total
510
510
587
357
429
Memory Blocks
1
1
1
1
1
Device
AFS600
A3PE600
APA075
AX125
RTAX250S
Utilization
4%
4%
19%
18%
10%
Device Utilization for One Rx Module
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
Combinatorial
431
431
588
307
350
Sequential
233
233
236
234
259
Total
664
664
824
541
609
Memory Blocks
2
2
2
2
2
Devices
AFS600
A3PE600
APA075
AX125
RTAX250S
Utilization
5%
5%
27%
27%
14%
v5.0
3
ARINC 429 Bus Interface
Table 3 •
Device Utilization for One Rx and One Tx Module
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
Table 4 •
Combinatorial
848
848
1,084
518
604
Sequential
609
609
377
378
429
Total
1,457
1,457
1,461
896
1,033
Memory Blocks
3
3
3
3
3
Device
AFS600
A3PE600
APA075
AX125
RTAX250S
Utilization
10%
10%
48%
44%
24%
Device Utilization for 16 Rx and 16 Tx Modules
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
Table 5 •
Combinatorial
13,435
13,435
16,835
8,044
9,594
Sequential
9,614
9,614
5,928
5,944
6,745
Total
23,049
23,049
22,763
13,988
16,339
Memory Blocks
48
48
48
48
48
Device
AFS1500
A3PE1500
APA750
AX2000
RTAX2000S
Utilization
60%
60%
69%
43%
51%
Device Utilization for Legacy Mode (2 Rx and 1 Tx)
Cells or Tiles
Memory
Blocks
5
5
5
5
5
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
Combinational
1,444
1,444
1,840
955
1,062
Sequential
1,068
1,068
674
653
729
Total
2,512
2,512
2,514
1,608
1,791
Device
AFS600
A3PE600
APA150
RTAX250S
RTAX250S
Utilization
18%
18%
41%
20%
42%
Core429 clock rate can be programmed to be 1, 10, 16, or
20 MHz. All the Actel families listed above easily meet
the required performance.
Core429 I/O requirements depend on the system
requirements and the external interfaces. If the core and
memory blocks are implemented within the FPGA and
the CPU interface has a bidirectional data bus, then
approximately 74 I/O pins are required to implement
four Rx and four Tx modules. The core will require 62
pins to implement one Rx and one Tx module.
The core has various FIFO flags available for debugging
purposes. These flags may not be needed in the final
design and this will reduce the I/O count.
Memory Requirements
The number of memory blocks required differs, depending on whether each channel is configured the same or
differently.
Each Channel Configured the Same
Use
EQ 1
to calculate the number of memory blocks required if each channel is configured the same.
Number of memory blocks = NRx * (INT (LABEL_SIZE/X) + INT (RX_FIFO_DEPTH/Y) + NTx * INT (FIFO_DEPTH/Y),
EQ 1
4
v5.0
ARINC 429 Bus Interface
where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up
to the next integer, and X and Y are defined in
Table 6.
Each Channel Configured Differently
Use
EQ 2
to calculate the number of memory blocks required if each channel is configured differently.
NTx
–
1
NRx
–
1
Number of memory blocks =
∑
I
=
0
INT(FIFO_DEPTH[I]/Y +
∑
I
=
0
(INT(LABEL_SIZE[I]/X) + INT(FIFO_DEPTH[I]/Y)),
EQ 2
where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up
to the next integer, and X and Y are defined in
Table 6.
Table 6 •
Memory Parameters
X
512
512
256
512
Y
128
128
64
128
Device Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator/RTAX-S
Examples for the ProASIC3/E Device Family
If the design has 2 receivers, 1 transmitter, 64 labels for each receiver, 32-words-deep FIFO for each receiver and
transmitter, then
the number of memory blocks = 2 * (INT (64/512) + INT (32/128)) + 1 * INT (32/128) = 2 * (1 + 1) + 1 * (1) = 5.
If the design has 2 receivers, 1 transmitter, 32 labels for receiver # 1, 64 labels for receiver # 2, 32 words-deep FIFO for
receiver # 1, 64-words-deep FIFO for receiver # 2, and 64-words-deep FIFO for transmitter, then
the number of memory blocks = INT (64/128) + (INT (32/512) + INT (32/128)) + (INT (64/512) + INT (64/128))
= 1 + (1 + 1) + (1 + 1) = 5.
Core429 Overview
Core429 provides a complete and flexible interface to a
microprocessor and an ARINC 429 data bus. Connection
to an ARINC 429 data bus requires additional line drivers
and line receivers.
Core429 interfaces to a processor through the internal
memory of the receiver. Core429 can be easily interfaced
to an 8-, 16- or 32-bit data bus. Look-up tables loaded
into memory enable the Core429 receive circuitry to
filter and sort incoming data by label and destination
bits. Core429 supports multiple (configurable) ARINC 429
receiver channels, and each receives data independently.
The receiver data rates (high or low speed) can be
programmed independently. Core429 can decode and
sort data based on the ARINC 429 Label and SDI bits and
stores it in FIFO. Each receiver uses programmable FIFO
to buffer received data. Core429 supports multiple
(configurable) ARINC 429 transmit channels and each
channel can transmit data independently.
Default Mode
This is the recommended mode and allows the user to
configure the core with user-defined transmit and
receive channels.
Functional Description
The core has three main blocks: Transmit, Receive, and
CPU interface. The core can be configured to provide up
to 16 transmit and receive channels.
v5.0
5
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