Datasheet> 器件分类 > 无线/射频/通信> 电信电路> T-8503-EL2-DT

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T-8503-EL2-DT: 产品描述Codec,; 产品类别无线/射频/通信电信电路; 文件大小28KB，共2页; 制造商LSC/CSI; 官网地址https://lsicsi.com

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T-8503-EL2-DT概述

Codec,

T-8503-EL2-DT规格参数

参数名称	属性值
包装说明	,
Reach Compliance Code	unknown
Base Number Matches	1

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Product Brief

February 2002

T8502 and T8503 Dual PCM Codecs with Filters

Features

5 V only

Two independent channels

Pin-selectable receive gain control

Pin-selectable µ-law or A-law companding

Automatic powerdown mode

Low-power, latch-up-free CMOS technology

— 40 mW/channel typical operating power

dissipation

— 12.5 mW/channel typical standby power

dissipation

Automatic master clock frequency selection

— 2.048 MHz or 4.096 MHz

Independent transmit and receive frame strobes

2.048 MHz or 4.096 MHz data rate

On-chip sample and hold, autozero, and precision

voltage reference

Differential architecture for high noise immunity

and power supply rejection

Meets or exceeds ITU-T G.711—G.712 require-

ments and VF characteristics of D3/D4 (as per

Agere Systems Inc.’s PUB43801)

Operating temperature range: –40 °C to +85 °C

The T8502 differs from the T8503 in its timing mode.

The T8502 operates in the delayed timing mode

(digital data is valid one clock cycle after frame sync

goes high), and the T8503 operates in the

nondelayed timing mode (digital data valid when

frame sync goes high).

Two channels of PCM data input and output are

passed through only two ports, D

and D

, so some

type of time-slot assignment is necessary. The

scheme used here is to utilize a fixed-data rate mode

of 32 or 64 time slots corresponding to master clock

frequencies of either 2.048 MHz or 4.096 MHz,

respectively. Each device has four frame sync (FS

and FS

) inputs, one pair for each channel. During a

single 125 µs frame, each frame sync input is sup-

plied a single pulse. The timing of the respective

frame sync pulse indicates the beginning of the time

slot during which the data for that channel is clocked

in or out of the device. FS

and FS

must be high for

a minimum of one master clock cycle. They can be

operated independently, or they can be tied together

for coincident transmit and receive data transfer. Dur-

ing a frame, channel 0 and 1 transmit frame sync

pulses must be separated from each other by one or

more time slots. Likewise, channel 0 and 1 receive

frame sync pulses must be separated from each

other by one or more time slots. Both transmit and

receive frame strobes must be derived from master

clock, but they do not need to be byte aligned.

A channel is placed in standby mode by removing

both FS

and FS

for 500 µs. Note, if any one of

those pulses (per channel) is removed, operation is

indeterminate. Standby mode reduces overall device

power consumption by turning off nonessential cir-

cuitry. Critical circuits that ensure a fast, quiet pow-

erup are kept active. Master clock need not be active

when both channels are in standby mode.

The frequency of the master clock must be either

2.048 MHz or 4.096 MHz. Internal circuitry deter-

mines the master clock frequency during the pow-

erup reset interval.

Description

The T8502 and T8503 devices are single-chip, two-

channel, µ-law/A-law PCM codecs with filters. These

integrated circuits provide analog-to-digital and

digital-to-analog conversion. They provide the

transmit and receive filtering necessary to interface a

voice telephone circuit to a time-division multiplexed

system. These devices are packaged in both 20-pin

SOJs and 20-pin SOGs.

T-8503-EL2-DT相似产品对比

	T-8503-EL2-DT	T-8503-EL2-D
描述	Codec,	PCM Codec, A/MU-Law, 2-Func, CMOS, PDSO20,
Reach Compliance Code	unknown	unknown
Base Number Matches	1	1

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