M13X Device
DS3/DS1 MUX/DEMUX, Enhanced Features
TXC-03305
DATA SHEET
FEATURES
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Multiplexes/demultiplexes 28 DS1 signals to/from
a DS3 signal
Integrated dejitter buffers to GR-499-CORE for
all receive DS1 outputs, with bypass option
M13 or C-bit parity format mode operation
FEBE, C, or P-bit parity error insertion capability
DS3 idle signal generators
DS1 idle signal (QRS, AIS or ESF) generators
DS3 LOS, LOF, P-bit parity, C-bit parity, AIS and
idle detectors
Integrated PMDL controller
Receive or transmit DS1 LOS detectors
DS2 LOF detectors
External interface for receiving 14 C-bits and
transmitting either 13 or 14 C-bits based on a
control bit setting
DS3 and DS2 X-bit access
DS3 transmit and receive selectable AIS
generation and detection
Supports Intel, Motorola, or multiplexed
microprocessor interfaces, and includes interrupt
capability
DS2 transmit/receive X-bit control/status
8 or 16-bit wide performance counters
Reset lead
Test Access Port for boundary scan
Single +5V,
±5%
power supply
208-lead Small Outline Plastic BGA package or
208-lead PQFP package (for M13E replacement)
DESCRIPTION
The M13X CMOS VLSI device provides the functions needed to
multiplex and demultiplex 28 independent DS1 signals to and from
a DS3 signal with either an M13 or C-bit frame format. It includes
some enhanced features relative to the M13E device. A lead
(M13X) is provided for selecting functional and software backwards
compatibility with the M13E device (TXC-03303). The M13X line
side signals typically interface with a TranSwitch ART, ARTE or
DART device, a DS3LIM-SN module or other DS3 line circuitry. Ter-
minal side signals interface with commercially available DS1 line
interface devices or a TranSwitch T1Fx8 device for DS1 framing.
The output DS1 signals can optionally be dejittered via integrated
dejitter buffers (DJBs). The DJBs meet and exceed the require-
ments specified in GR-499-CORE, 1998.
The M13X provides an external transmit (13 or 14 bits) and receive
(14 bits) interface for the 21 C-bits while operating in the C-bit parity
mode. The FEAC channel (C3) can be accessed via the external
interface or the M13X memory. An integrated PMDL controller is
provided for transmitting and receiving HDLC encapsulated PMDL
messages. Buffering of PMDL messages is provided in the transmit
and receive directions. Message lengths of arbitrary size can be
transmitted or received. The M13X memory map contains up to 64
8-bit register locations for software control, performance counters,
and alarm reporting. The microprocessor interface provides for
connection to an Intel or Motorola-compatible microprocessor, or
for use of a multiplexed address/data bus. An interrupt lead with
programmable polarity is provided.
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APPLICATIONS
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Single-board M13 multiplexer
Compact add/drop mux
Fractional T3
Channelized T3
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LINE SIDE
DS3 Receive
Clock and Data
+5V
M13X Lead
TERMINAL SIDE
DS1
Channel 28 I/O
Clock and Data
M13X
DS3/DS1
MUX/DEMUX,
Enhanced Features
TXC-03305
DS3 Transmit
Clock and Data
DS1
Channel 1 I/O
Clock and Data
Test Address
Access Strap
C-bits I/O
Microprocessor Port
Leads Data, Clock,
Bus
and Frame
Copyright
2000 TranSwitch Corporation
M13X is a trademark of TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
TXC-03305-MB
Ed. 4, September 2000
TranSwitch Corporation
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3 Enterprise Drive
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Shelton, Connecticut 06484
Tel: 203-929-8810
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Fax: 203-926-9453
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www.transwitch.com
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USA
M13X
TXC-03305
DATA SHEET
TABLE OF CONTENTS
Section
Page
Block Diagram ................................................................................................................... 4
Block Diagram Description ................................................................................................ 5
Lead Diagrams .................................................................................................................. 8
Lead Descriptions ........................................................................................................... 10
Power Supply, Ground, and no Connect ................................................................. 10
Ds1 Receive Interfaces ............................................................................................ 11
Ds1 Transmit Interfaces .......................................................................................... 13
Ds3 Interface ............................................................................................................ 15
Microprocessor Interface .......................................................................................... 16
Transmit C-bit Interface ............................................................................................ 20
Control Leads ........................................................................................................... 21
External Clock .......................................................................................................... 21
Test Access Port ...................................................................................................... 22
Scan Test Leads ....................................................................................................... 22
Absolute Maximum Ratings And Environmental Limitations .......................................... 23
Thermal Characteristics .................................................................................................. 23
Power Requirements ....................................................................................................... 23
Input, Output and Input/Output Parameters .................................................................... 24
Timing Characteristics ..................................................................................................... 26
Operation ........................................................................................................................ 39
M13X Lead ............................................................................................................... 39
Resets ...................................................................................................................... 40
Integrated DJB Devices ............................................................................................ 41
Jitter Tolerance ......................................................................................................... 42
Jitter Transfer ........................................................................................................... 45
Jitter Generation ....................................................................................................... 48
Jitter Enhancement ................................................................................................... 48
Residual Jitter ........................................................................................................... 48
Interrupts .................................................................................................................. 49
PMDL Operation ....................................................................................................... 50
Counters ................................................................................................................... 55
C-bit Interfaces ......................................................................................................... 56
Test Access Port ...................................................................................................... 57
Software Initialization Sequence ..................................................................................... 66
System Considerations ............................................................................................. 66
Memory Map ................................................................................................................... 67
Memory Map Descriptions .............................................................................................. 69
Application Diagram ........................................................................................................ 95
Package Information ....................................................................................................... 96
Ordering Information ....................................................................................................... 98
Related Products ............................................................................................................. 98
Standards Documentation Sources .............................................................................. 100
List of Data Sheet Changes .......................................................................................... 102
Documentation Update Registration Form *
............................................................. 106
* Please note that TranSwitch provides documentation for all of its products. Customers who are
using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing
Department to receive relevant updated and supplemental documentation as it is issued. They
should also contact the Applications Engineering Department to ensure that they are provided
with the latest available information about the product, especially before undertaking
development of new designs incorporating the product.
TXC-03305-MB
Ed. 4, September 2000
-2-
DATA SHEET
LIST OF FIGURES
Figure
M13X
TXC-03305
Page
1M13X TXC-03305 Block Diagram ................................................................................... 4
2C-Bit Assignments ........................................................................................................... 7
3M13X TXC-03305 Lead Diagram for PBGA Package ..................................................... 8
4M13X TXC-03305 Lead Diagram for PQFP Package ..................................................... 9
5DS3 Receive Timing ......................................................................................................26
6DS3 Transmit Timing ..................................................................................................... 27
7DS1 Receive Timing with DJBs Disabled ....................................................................... 28
8DS1 Receive Timing with DJBs Enabled ....................................................................... 28
9DS1 Transmit Timing ......................................................................................................29
10C-Bit Receive Interface Timing..................................................................................... 30
11C-Bit Transmit Interface Timing ................................................................................... 31
12Microprocessor Read Cycle Timing - Multiplexed Interface ........................................ 32
13Microprocessor Write Cycle Timing - Multiplexed Interface ........................................ 33
14Microprocessor Read Cycle Timing - Intel Interface .................................................... 34
15Microprocessor Write Cycle Timing - Intel Interface .................................................... 35
16Microprocessor Read Cycle Timing - Motorola Interface ............................................ 36
17Microprocessor Write Cycle Timing - Motorola Interface ............................................. 37
18Boundary Scan Timing ................................................................................................ 38
19M13X Reset Structure ................................................................................................. 40
20DS1 Input Jitter Tolerance ........................................................................................... 43
21DS3 Input Jitter Tolerance ........................................................................................... 44
22DS3 to DS1 Interface Jitter Transfer Limits ................................................................. 46
23DS1 to DS1 Jitter Transfer Limits ................................................................................ 47
24HDLC Format .............................................................................................................. 50
25Boundary Scan Schematic .......................................................................................... 58
26Example Channelized T3 Application .......................................................................... 95
27M13X TXC-03305 208-Lead Plastic Ball Grid Array Package .....................................96
28M13X TXC-03305 208-Lead Plastic Quad Flat Package ............................................ 97
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TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
BLOCK DIAGRAM
DATA SHEET
A block diagram for the M13X device is shown in Figure 1 below.
7
DS3DR
DS3CR
CDR
CCKR
CFMR
CDCCR
DS3 Local Loopback
XCK
DLEN
OUTDIS
HRESET
M13X
7
TXFRM
DS3DT
DS3CT
CDT
CCKT
CFMT
CDCCT
DS3
Framing/Stuffing/PMDL
DS2
Framing/Stuffing
Test Access Port
1
Alarm/Status
Control
DS3
Frame Sync
DS3
Destuffing/PMDL
1
DS2
Sync/Destuff
28
1 DS1
Outputs
DJB
DR28
DR1
CR28
CR1
DS1
Micro-
Local
processor
Loopbacks Interface
Micro-
processor
I/O and
Memory
Map
S7
S6
S5
28
1
DS1
Input
DT28
DT1
CT28
CT1
GND
VDD
TMS TDI TDO TCK TRS
Figure 1. M13X TXC-03305 Block Diagram
TXC-03305-MB
Ed. 4, September 2000
-4-
DATA SHEET
BLOCK DIAGRAM DESCRIPTION
M13X
TXC-03305
Figure 1 shows a simplified block diagram of the M13X and its signal leads. The M13X is packaged in a 208-
lead small outline Plastic Ball Grid Array (PBGA) package or a 208-lead Plastic Quad Flat Package (PQFP).
The PQFP version is intended to be used as a replacement for TranSwitch’s M13E device (TXC-03303-AIPQ)
and is not recommended for new designs. The PBGA version is intended for new designs.
The M13X in the PBGA or PQFP packages, with the exception of the boundary scan, can be configured to be
functionally compatible with, and have the same memory map as, the M13E device, by applying a high to the
M13X lead. The enhanced features included in the M13X can be enabled by applying a low to the M13X lead.
These enhanced M13X features are:
• Transmit/receive
PMDL (Path Maintenance Data Link) controller
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Interrupt request lead with programmable polarity and associated interrupt mask bits
Integrated dejitter buffer (DJB) on all receive DS1 outputs with optional bypass capability
16-bit performance counters.
NEW bit in register 1DH does not become set to one again after it is cleared when a constant FEAC message is
received.
When the M13X lead is set to high, the M13X enhanced features listed above are disabled and cannot be
accessed.
In the receive direction, DS3 data (DS3DR) is clocked into the M13X on rising edges of the DS3 input clock
(DS3CR). The data and clock signals may be derived from any line interface unit such as TranSwitch’s ART,
ARTE, DART or DS3LIM-SN, or from other line circuitry.
The DS3 Frame Sync block searches for and locks to the DS3 frame, as specified in Bellcore GR-499-CORE
“Transport System Generic Requirements,” and in ANSI T1.107-1995. The M13X receiver monitors the DS3
signal for out of frame, loss of signal, a DS3 AIS, DS3 idle signal, P-bit parity, the state of the X-bits, and loss of
clock. The DS3 AIS detection mechanism is software selectable, with a choice of six detectors. These range
from full compliance to T1.107-1995 to unframed all ones AIS detection. Control bits are also provided in mem-
ory which allow all, some of, or none of the DS3 alarms to cause the insertion of AIS into the receive DS1
channels.
In the M13 format mode, destuffing from DS3 to DS2 is performed based on the states of the C-bits in the DS3
subframes. If two or three of the C-bits in a subframe are ones, the associated stuff bit is interpreted as being a
stuff bit and is removed from the data stream and discarded.
In the C-bit parity mode, the C-bits are allocated for network performance. The M13X performs Far End Alarm
and Control (FEAC) detection, C-bit parity error detection, and Far End Block Error (FEBE) detection. FEAC
loopback requests and alarm/status information are provided in the memory map. In addition, the states of 14
C-bits (C2, C3, C4, C5, C6, C13, C14, C15, C16, C17, C18, C19, C20, and C21) are provided at a serial inter-
face (CDR), along with an output clock signal (CCKR), framing pulse (CFMR), and data link indicator pulse
(CDCCR). The data link indicator pulse identifies the location of the data link bits, C13, C14, and C15. If the
M13X lead is tied low, the receive PMDL (Path Maintenance Data Link) controller can be enabled via a control
bit. The receive PMDL controller is used to extract PMDL messages of any length. FCS error detection,
ABORT detection, End of Message, Start of Message, Invalid Frame Detected, and receive PMDL FIFO status
can be monitored via the microprocessor interface.
The M13X synchronizes and extracts the 28 DS1 channels from the seven DS2 channels. Each of the DS2
channels is monitored for out of frame. The M13X may generate AIS in each of the DS1 signal tributaries cor-
responding to the DS2 channel(s) that lost frame, depending on the DS1 AIS alarm insertion control bits. DS2
to DS1 destuffing is based on the states of the three C-bits in each DS2 subframe. If two or three of the C-bits
in one of the DS2 subframes are ones, the stuff bit for that subframe is discarded. In the M13 format mode, the
DS2 C-bits or stuffing bits are used for DS1 remote loopback requests for either the M13 or C-bit Parity format
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TXC-03305-MB
Ed. 4, September 2000
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