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TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
D
D
D
D
Single-Chip Receiver/Transmitter for
Transporting 53-Byte Asynchronous
Transport Mode (ATM) Cells Via
STS-3c/STM-1 Frame (155.52 Mbit/s)
On-Chip Analog Phase-Locked Loop
(APLL) Provides:
– Recovery of Receive Clock From
Incoming Serial-Data Stream
– Transmit Clock Generation From
External 19.44-MHz Clock Source
Inserts and Extracts ATM Cells Into/From
SONET/SDH STS-3c/STM-1 SPE
Detects Multiple-Bit Errors and Corrects
Single-Bit Errors in the 5-Byte ATM
Headers of Incoming ATM Cells
D
D
D
Generates Alarms for:
– Loss of Incoming Serial Signal (LOS)
– Out of Frame (OOF)
– Loss of Frame (LOF)
– B1-Byte Parity Error (B1ERR)
– Loss of ATM Cell Alignment (LOCA)
– Line Far-End Receive Failure (LFERF)
– Receive Loss of Pointer (LOP)
– Line Alarm Indication Signal (LAIS)
Meets ATM Forum ATM User-Network
Interface Specification Requirement
Package Options Include 144-Pin Plastic
Quad Flat (PCM) and 144-Pin Thin Quad
Flat (PGE) Packages
description
The synchronous optical network (SONET)/synchronous digital hierarchy (SDH) asynchronous transport mode
(ATM) line-interface receiver/ transmitter provides a single-chip implementation for transporting ATM cells over
the SONET/SDH network at the STS-3c/STM-1 rate of 155.52 Mbits/s. This device provides all the functionality
required to insert and extract 53-byte ATM cells into/from an STS-3c/STM-1 synchronous payload envelope
(SPE), including clock recovery and clock generation using analog phase-locked loops (APLL).
On the receive side, the TNETA1500A accepts 155.52-Mbit/s serial data, recovers the embedded clock signal,
performs SONET/SDH frame alignment and serial-to-parallel conversion, identifies the SONET/SDH payload,
and establishes the ATM-cell boundaries. The ATM cells are extracted from the payload, descrambled, and
passed to the receive output FIFO for output to the next device (i.e., a reassembly device). On the transmit side,
complete 53-byte ATM cells are placed in the transmit input FIFO, scrambled, and inserted into an
STS-3c/STM-1 SPE. The SONET/SDH frame is scrambled and converted to a serial-data stream for output.
An APLL is used to generate the 155.52-MHz output clock from a low-speed 19.44-MHz oscillator, eliminating
the need for a high-speed 155.52-MHz oscillator.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
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1
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
PCM OR PGE PACKAGE
(TOP VIEW)
AV CC
AGND
AVCC
RSCC
RSCT
FLAGT
FLAGC
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
V CC
GND
RD/WR
SEL
READY
INTR
V CC
GND
D7
D6
D5
D4
VCC
GND
D3
D2
D1
D0
35
CRCAP
AGND
AGND
AVCC
RSDT
RSDC
AVCC
AGND
AGND
CGCAP
AVCC
TXREFCK
TXHCKT
TXHCKC
TSDT
TSDC
TSCT
TSCC
AVCC
AGND
SDHENABLE
OE
TEST0
TEST1
TXAF
GND
TXCELL
TWE
TCKI
GND
V CC
TD0
TD1
TD2
TD3
GND
30
25
20
15
10
5
1
GND
V CC
RESET
TEST4
TEST3
TEST2
FLB
TLB
CKGENBP
CKRECBP
CLKLOOP
LOF
GND
V CC
8KHZREF
OOF
LOS
GND
V CC
B1ERR
LOCA
LFERF
LAIS
LOP
RCKI
RRE
RXFE
RXCELL
LOSRD
GND
V CC
NC
NC
NC
NC
GND
40
140
45
135
50
130
55
125
60
120
65
115
70
110
75
TD4
TD5
TD6
TD7
V CC
80
85
90
95
100
105
NC – No internal connection
2
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GND
RD0
RD1
RD2
RD3
V CC
GND
RD4
RD5
RD6
RD7
V CC
GND
NC
NC
NC
NC
V CC
GND
NC
NC
NC
NC
V CC
GND
NC
NC
NC
NC
V CC
V CC
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
functional block diagram
CRCAP
330-pF Capacitor
Connected Externally
FLB
RSDT
RSDC
CKRECBP
RSCT
RSCC
CLKLOOP
8
8
OE
Controller
Interface
D0–D7
A0–A7
READY
RD/WR
INTR
SEL
FLAGT
FLAGC
Clock
Recovery
Framing and
Serial-to-Parallel
Conversion
Descrambling,
B1-Parity,
Alarm
Generation
ATM-Cell
Extraction
and
Descrambling
8KHZREF LOF LOS OOF
B1ERR
LAIS
Receive Operation
LOP
LFERF
LOSRD
LOCA
8
Demux
RD0–RD7
RCKI
RXCELL
RRE
RXFE
RESET
TSDT
TSDC
TSCT
TSCC
TLB
CKGENBP
TXREFCK
TXHCKT
TXHCKC
Clock
Generation
CGCAP
Parallel-to-Serial
Conversion
8
Scrambling
and
B1-Parity
Generation
Transmit Operation
SDHENABLE
0.01-µF Capacitor
Connected Externally
Mux
ATM-Cell
Scrambling
and
Cell Insertion
TD0–TD7
TCKI
TXCELL
TWE
TXAF
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3
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
detailed description
transmit operation
The transmit-cell interface consists of the byte-wide input data (TD0–TD7), input clock (TCKI), start of ATM-cell
input (TXCELL), transmit write-enable input (TWE), and transmit-input FIFO almost-full output (TXAF). Input
data is clocked into the TNETA1500A on low-to-high transitions of TCKI when TWE is low. The transmit-input
FIFO almost-full flag (TXAF) goes active when the transmit FIFO is within five bytes of filling up (the FIFO holds
three complete ATM cells).
The 48-byte information field of the ATM cell is scrambled using a self-synchronizing scrambler polynomial of
x
43
+ 1 to improve the efficiency of the cell-delineation procedure. At startup, the scrambler is initialized to an
all-1s state. The 5-byte ATM header is not scrambled at this step. TXCELL identifies the first byte of the ATM
cell and disables the scrambler. The input data is stored in the transmit-input FIFO and multiplexed into the
SONET/SDH payload after all 53 bytes have been received. If the FIFO does not contain 53 bytes of information
at the start of a cell-insertion cycle, an idle or unassigned cell is sent, dependent on the status of the control
registers. An idle cell is defined as an ATM cell with the 5-byte header set to 00 00 00 01 52 (hex) and the 48-byte
payload set to 6A (hex). An unassigned cell is defined as an ATM cell with the 5-byte header set to
00 00 00 00 55 (hex) and the 48-byte payload set to 6A (hex). See
controller-interface operation
for more
information on the operation of the control registers.
The transmit section calculates the header-error-check (HEC) byte in the ATM header by default. This implies
that the fifth byte of the ATM cell that is input through the transmit-cell interface is ignored. The HEC byte is
calculated in accordance with the ANSI T1.624-1993 and CCITT recommendation I.432. This feature can be
disabled by setting a bit in the control register.
The transmit operation can be programmed to send either a SONET STS-3c frame or an SDH STM-1 frame.
When SDHENABLE is low, a SONET STS-3c frame is transmitted. When SDHENABLE is high, an STM-1 frame
is transmitted. For both the STS-3c and STM-1 frames, the location of the J1 byte in the path overhead is fixed;
the J1 byte always comes after the third C1 byte of the transport overhead (TOH). This is known as location 522.
The data-communication channels (D1 through D12 bytes) in the TOH are set to a hex value of FF 00 00. The
values for the transport- and path-overhead bytes for both an STS-3c frame and an STM-1 frame are given in
Table 1.
The parity bytes B1, B2 (three bytes), and B3 are calculated as follows:
B1 — B1 is a bit-interleaved parity-8 (BIP-8) code using even parity. B1 is calculated over all bits of the
previous STS-3c frame after scrambling. The calculated value of B1 is placed in the STS-3c frame before
the frame is scrambled.
B2 — For an STS-3c frame, the three B2 bytes combine to form a BIP-24 code; however, each B2 byte is
calculated as if the frame is composed of three individual STS-1s. Each B2 is calculated over all bits of the
line overhead and STS-1 envelope capacity of the previous STS-1 frame before scrambling, using even
parity. The computed value is placed in the appropriate B2 byte location before scrambling. The line
overhead consists of the six rows of TOH bytes, beginning with the first H1 byte and ending before the row
containing the first A1 byte (see Table 1).
B3 — For an STS-3c frame, the B3 byte is calculated over all bits of the previous STS-3c SPE before
scrambling. B3 is a BIP-8 code, using even parity. The computed value is placed in the B3 location
before scrambling.
4
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