Final Electrical Specifications
LT1949-1
1.1MHz, 1A Switch
PWM DC/DC Converter
June 2000
DESCRIPTIO
FEATURES
s
s
s
s
s
s
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s
1A, 0.5Ω, 30V Internal Switch
1.1MHz Fixed Frequency Operation
Operates with V
IN
as Low as 1.5V
Low-Battery Detector Stays Active in Shutdown
Low V
CESAT
Switch: 410mV at 800mA
Pin-for-Pin Compatible with the LT1317B
Uses Ceramic Capacitors
Small 8-Lead MSOP Package
APPLICATIO S
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The LT
®
1949-1 is a fixed frequency step-up DC/DC con-
verter with a 1A, 0.5Ω internal switch. Capable of gener-
ating 10V at 175mA from a 3.3V input, the LT1949-1 is
ideal for generating bias voltages for large screen LCD
panels. Constant frequency 1.1MHz operation results in a
low noise output that is easy to filter and the 30V switch
rating allows output voltage up to 28V using a single
inductor. The high switching frequency allows the use of
ceramic output capacitors. An external compensation pin
gives the user flexibility in optimizing loop compensation,
allowing small, low ESR ceramic capacitors to be used at
the output. The 8-lead MSOP package ensures a low
profile overall solution.
The LT1949-1 includes a low-battery detector that stays
alive when the device goes into shutdown. Quiescent
current in shutdown is 50µA, while operating current is
8mA.
, LTC and LT are registered trademarks of Linear Technology Corporation.
LCD Bias Supplies
GPS Receivers
Battery Backup
Portable Electronic Equipment
Diagnostic Medical Instrumentation
TYPICAL APPLICATIO
V
IN
3.3V
C1
3.3µF
CERAMIC
SHUTDOWN
V
IN
LT1949-1
SHDN
V
C
84.5k
50pF
L1
4.7µH
90
D1
SW
V
OUT
= 10V
80
70
EFFICIENCY (%)
V
OUT
10V
175mA
R1
196k
1%
FB
GND
3pF
60
50
40
R2
28k
1%
C2
3.3µF
CERAMIC
30
20
C1, C2: TAIYO YUDEN LMK325BJ335MD
D1: MBRM120LT3
L1: SUMIDA CLQ4D10-4R7
1949-1 F01
5
10
Figure 1. 3.3V to 10V/175mA DC/DC Converter
Figure 2. 3.3V to 10V Converter Efficiency
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
3.6V
IN
4.2V
IN
3V
IN
50
100
LOAD CURRENT (mA)
300
1949-1 F02
U
U
1
LT1949-1
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
V
C
FB
SHDN
GND
1
2
3
4
8
7
6
5
LBO
LBI
V
IN
SW
V
IN
, LBO Voltage ..................................................... 12V
SW Voltage ............................................... – 0.4V to 30V
FB Voltage .................................................... V
IN
+ 0.3V
V
C
Voltage ................................................................ 2V
LBI Voltage ............................................ 0V
≤
V
LBI
≤
1V
SHDN Voltage ........................................................... 6V
Junction Temperature .......................................... 125°C
Operating Temperature Range (Note 2) ...–40°C to 85°C
Storage Temperature ........................... – 65°C to 150°C
Lead Temperature (Soldering, 10sec).................. 300°C
ORDER PART
NUMBER
LT1949-1EMS8
MS8 PART MARKING
LTQX
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 120°C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL
I
Q
V
FB
I
B
g
m
A
V
PARAMETER
Quiescent Current
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN
= 2V, V
SHDN
= 2V unless otherwise noted.
CONDITIONS
V
SHDN
= 0V
Feedback Voltage
q
q
q
MIN
TYP
8
50
MAX
14
80
1.26
1.26
150
12
480
UNITS
mA
µA
V
V
nA
V
µmhos
V/V
%
1.22
1.20
1.7
140
80
1
0.85
1.24
1.24
24
280
700
85
1.1
1.1
0.015
–5
FB Pin Bias Current (Note 3)
Input Voltage Range
Error Amp Transconductance
Error Amp Voltage Gain
Maximum Duty Cycle
Switch Current Limit (Note 4)
V
IN
= 2.5V, Duty Cycle = 30%
∆I
= 5µA
q
q
q
q
1.5
1.35
0.1
– 14
210
220
0.25
100
120
3
400
6
0.4
f
OSC
Switching Frequency
Shutdown Pin Current
LBI Threshold Voltage
V
SHDN
= V
IN
V
SHDN
= 0V
q
q
q
q
190
180
200
200
0.15
20
30
2000
0.01
410
270
0.08
LBO Output Low
LBO Leakage Current
LBI Input Bias Current (Note 5)
Low-Battery Detector Gain
Switch Leakage Current
Switch V
CESAT
Reference Line Regulation
SHDN Input Voltage High
SHDN Input Voltage Low
I
SINK
= 10µA
V
LBI
= 250mV, V
LBO
= 5V
V
LBI
= 150mV
1MΩ Pull-Up
V
SW
= 5V
I
SW
= 800mA
I
SW
= 500mA
1.8V
≤
V
IN
≤
12V
q
q
q
q
q
q
q
1.4
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
The LT1949-1E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3:
Bias current flows into FB pin.
Note 4:
Switch current limit guaranteed by design and/or correlation to
static tests. Duty cycle affects current limit due to ramp generator.
Note 5:
Bias current flows out of LBI pin.
2
U
A
MHz
µA
µA
mV
mV
V
nA
nA
V/V
µA
mV
mV
%/V
V
V
W
U
U
W W
W
LT1949-1
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
1.3
1.3
OSCILLATOR FREQUENCY (MHz)
85°C
25°C
SWITCH CURRENT (A)
SWITCH CURRENT (A)
1.2
1.1
–40°C
1.0
0.9
0
2
4
6
8
INPUT VOLTAGE (V)
Switch Voltage Drop (V
CESAT
)
1.0
1.25
QUIESCENT CURRENT (mA)
0.8
85°C
25°C
0.4
–40°C
0.2
FEEDBACK VOLTAGE (V)
SWITCH VOLTAGE (V)
0.6
0
0
0.2
0.4
0.6
0.8
SWITCH CURRENT (A)
1.0
1.2
Quiescent Current, SHDN = 0V
60
55
QUIESCENT CURRENT (µA)
FB PIN BIAS CURRENT (nA)
50
45
40
35
30
–50
45
40
35
30
25
20
15
SHDN PIN CURRENT (µA)
–25
0
25
50
TEMPERATURE (°C)
U W
10
12
1949-1 G01
1949-1 G04
Switch Current Limit
1.3
Switch Current Limit,
Duty Cycle = 30%
1.2
1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8
0
20
60
40
DUTY CYCLE (%)
80
100
1949-1 G02
0.8
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1949-1 G03
Feedback Voltage
8.5
8.0
Quiescent Current, SHDN = 2V
1.24
7.5
7.0
6.5
6.0
5.5
5.0
1.23
1.22
1.21
1.20
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4.5
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1949-1 G05
1949-1 G06
FB Pin Bias Current
60
55
50
1
2
SHDN Pin Current
0
–2
–4
75
100
10
–50
–6
–25
0
25
50
TEMPERATURE (°C)
75
100
0
1
4
3
SHDN PIN VOLTAGE (V)
2
5
6
1949-1 G09
1949-1 G07
1949-1 G08
3
LT1949-1
TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
V
OUT
100mV/DIV
AC COUPLED
PI FU CTIO S
V
C
(Pin 1):
Compensation Pin for Error Amplifier. Con-
nect a series RC network from this pin to ground. Typical
values for compensation are a 30k/330pF combination
when using ceramic output capacitors. Minimize trace
area at V
C
.
FB (Pin 2):
Feedback Pin. Reference voltage is 1.24V.
Connect resistor divider tap here. Minimize trace area at
FB. Set V
OUT
according to: V
OUT
= 1.24V(1 + R1/R2).
SHDN (Pin 3):
Shutdown. Pull this pin low for shutdown
mode (only the low-battery detector remains active).
Leave this pin floating or tie to a voltage between 1.4V and
6V to enable the device. SHDN pin is logic level and need
only meet the logic specification (1.4V for high, 0.4V for
low).
GND (Pin 4):
Ground. Connect directly to local ground
plane.
SW (Pin 5):
Switch Pin. Connect inductor/diode here.
Minimize trace area at this pin to keep EMI down.
V
IN
(Pin 6):
Supply Pin. Must be bypassed close to the
pin.
LBI (Pin 7):
Low-Battery Detector Input. 200mV refer-
ence. Voltage on LBI must stay between ground and
700mV. Low-battery detector remains active in shutdown
mode.
LBO (Pin 8):
Low-Battery Detector Output. Open collec-
tor, can sink 10µA. A 1MΩ pull-up is recommended.
4
U W
I
L
500mA/DIV
20µs/DIV
V
IN
= 3.3V
V
OUT
= 10V
40mA TO 140mA LOAD STEP
CIRCUIT FIGURE 1
1949-1 G10
U
U
U
LT1949-1
BLOCK DIAGRA
1.24V
REFERENCE
V
OUT
BIAS
R1
(EXTERNAL)
FB
RAMP
GENERATOR
1.1MHz
OSCILLATOR
Figure 3. LT1949-1 Block Diagram
OPERATIO
The LT1949-1 is a current mode, fixed frequency step-up
DC/DC converter with an internal 1A NPN power transis-
tor. Operation can best be understood by referring to the
Block Diagram.
At the beginning of each oscillator cycle, the flip-flop is set
and the switch is turned on. Current in the switch ramps
up until the voltage at A2’s positive input reaches the V
C
pin voltage, causing A2’s output to change state and the
switch to be turned off. The signal at A2’s positive input is
a summation of a signal representing switch current and
a ramp generator (introduced to avoid subharmonic oscil-
lations at duty factors greater than 50%). If the load
increases, V
OUT
(and FB) will drop slightly and the error
amplifier will drive V
C
to a higher voltage, causing current
in the switch to increase. In this way, the error amplifier
drives the V
C
pin to the voltage necessary to satisfy the
load. Frequency compensation is provided by an external
series RC network connected between the V
C
pin and
ground.
+
+
Σ
+
–
R2
(EXTERNAL)
W
LBI
+
FB
2
g
m
V
C
1
200mV
ENABLE
7
+
–
A4
LBO
8
–
ERROR
AMPLIFIER
+
–
SHDN
SHUTDOWN
3
A1
COMPARATOR
SW
5
FF
R
A2
COMPARATOR
S
Q
DRIVER
Q3
+
A=2
0.06Ω
–
4
GND
1949-1 BD
U
Layout Hints
The LT1949-1 switches current at high speed, mandating
careful attention to layout for proper performance.
You
will not get advertised performance with careless layouts.
Figure 4 shows recommended component placement for
a boost (step-up) converter. Follow this closely in your PC
layout. Note the direct path of the switching loops. Input
capacitor C1
must
be placed close (< 5mm) to the IC
package. As little as 10mm of wire or PC trace from C
IN
to
V
IN
will cause problems such as inability to regulate or
oscillation.
The ground terminal of output capacitor C2 should tie
close to Pin 4 of the LT1949-1. Doing this reduces dI/dt in
the ground copper which keeps high frequency spikes to
a minimum. The DC/DC converter ground should tie to the
PC board ground plane at one place only, to avoid intro-
ducing dI/dt in the ground plane.
5
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