Product Specification
PE4210
Product Description
The PE4210 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from 10 MHz to 3 GHz. This single-
supply switch integrates on-board CMOS control logic driven
by a simple, single-pin CMOS or TTL compatible control input.
Using a nominal +3-volt power supply, a typical input 1 dB
compression point of +14 dBm can be achieved. The PE4210
also exhibits input-output isolation of better than 35 dB at
1000 MHz and is offered in a small 8-lead MSOP package.
The PE4210 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
SPDT UltraCMOS™ RF Switch
10 MHz - 3 GHz
Features
Single 3-volt power supply
Low Insertion loss: 0.30 dB at
1000 MHz, 0.45 dB at 2000 MHz
High isolation of 35 dB at 1000 MHz,
25 dB at 2000 MHz
Typical input 1 dB compression point
of +14.5 dBm
Single-pin CMOS or TTL logic control
Packaged in a small 8-lead MSOP
Figure 1. Functional Diagram
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71-0014-01
Document No. 70-0037-06
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Figure 2. Package Type
8-lead MSOP
te
PE4210
Product Specification
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(Z
S
= Z
L
= 50
Ω)
Parameter
Operating Frequency
1
Insertion Loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Video Feedthrough
2
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
CTRL to 0.1 dB final value, 2 GHz
CTRL to 25 dB isolation, 2 GHz
34.5
24.5
36.5
25.5
22.5
15
Conditions
Min
10
0.30
0.45
35.5
25
37.5
26.5
24.5
16
200
90
2.5
Typ
Max
3000
0.40
0.60
Units
MHz
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
mV
pp
dBm
dBm
Input IP3
2000 MHz, 5 dBm
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Min
2.7
0.7x V
DD
Input 1 dB Compression
2000 MHz
13
30
14.5
33.5
Parameter
V
DD
Power Supply Voltage
I
DD
Power Supply Current (V
DD
= 3 V, V
CNTL
= 3)
Control Voltage High
Control Voltage Low
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Table 2. DC Electrical Specifications
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Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50
Ω
test set-up,
measured with 1 ns risetime pulses and 500 MHz bandwidth.
Typ
3.0
250
Max
3.3
500
Units
V
nA
V
O
0.3x V
DD
V
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UltraCMOS™ RFIC Solutions
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PE4210
Product Specification
Figure 3. Pin Configuration (Top View)
Pin 1
V
DD
1
2
8
7
RF1
CTRL
GND
4210
GND
RFC
3
4
6
5
GND
Exceeding absolute maximum ratings may cause
permanent damage. Functional operation should
be restricted to the limits in the DC Electrical
Specifications table. Operation between operating
range maximum and absolute maximum for
extended periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
RF2
Table 3. Pin Descriptions
Pin No.
1
Pin Name
V
DD
Description
Nominal 3 V supply connection. A bypass
capacitor (100 pF) to the ground plane
should be placed as close as possible to
the pin
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Common RF port for switch
1
RF2 port
1
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o
Max
4.0
V
DD
+ 0.3
+150
+85
18
Units
V
V
°C
°C
dBm
V
4
5
6
RFC
RF2
GND
le
3
GND
Table 5. Control Logic Truth Table
Control Voltage
Signal Path
RFC to RF1
RFC to RF2
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
RF1 port
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
7
GND
8
RF1
1
Note 1. All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
V
ESD1
Parameter/Conditions
Power Supply Voltage
Voltage on any input
Storage temperature range
Operating temperature range
Input power (50
Ω)
HBM ESD Voltage
200
Min
-0.3
-0.3
-65
-40
Control Logic
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
O
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE4210 in the 8-lead 3 x 3 mm MSOP package is
MSL1.
Note: 1. Human Body Model ESD Voltage (HBM, MIL_STD 883 Method 3015.7)
Document No. 70-0037-06
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2
CTRL
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
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PE4210
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4210 SPDT switch. The RF common port is
connected through a 50
Ω
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
Ω
transmission lines to the top
two SMA connectors on the right side of the board,
J3 and J4. A through transmission line connects
SMA connectors J6 and J8. This transmission line
can be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide model with a trace width of
0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and
ε
r
of 4.4. Note
that the predominate mode for these transmission
lines is coplanar waveguide with a ground plane.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J2-3) is connected to the
device CTRL input. The fourth pin to the right (J2-7)
is connected to the device V
DD
input. A decoupling
capacitor (100 pF) is provided on both CTRL and
V
DD
traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
Figure 4. Evaluation Board Layout
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101-0037
102-0035
Figure 5. Evaluation Board Schematic
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Document No. 70-0037-06
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UltraCMOS™ RFIC Solutions
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PE4210
Product Specification
Typical Performance Data @ -40 °C to 85 °C (unless otherwise noted)
Figure 6. Insertion Loss – RFC to RF1
Figure 7. Input 1 dB Compression Point & IIP3
0
IIP3
-40 C
-0.25
40
-40 C
40
25 C
1 dB Compression Point (dBm)
Insertion Loss (dB)
-0.5
25 C
85 C
IIP3 (dBm)
30
85 C
30
-0.75
20
20
-1
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25 C
10
1dB Compression
-40 C
10
-1.25
-1.5
0
500
1000
1500
2000
2500
3000
le
0
500
1000
1500
Frequency (MHz)
2000
0
2500
Frequency (MHz)
Figure 8. Insertion Loss – RFC to RF2
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o
-40 C
2500
3000
Figure 9. Isolation – RFC to RF1
T = 25 °C
O
25 C
85 C
Isolation (dB)
0
0
-0.25
-20
Insertion Loss (dB)
-0.5
-40
-0.75
-60
-1
-80
-1.25
-1.5
0
500
1000
1500
2000
-100
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
Frequency (MHz)
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