without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00B
11/15/04
1
IS24C01B
IS24C02B
ISSI
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
®
FUNCTIONAL BLOCK DIAGRAM
Vcc
8
SDA
SCL
WP
5
7
X
DECODER
6
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
EEPROM
ARRAY
A0
A1
A2
1
2
3
WORD ADDRESS
COUNTER
Y
DECODER
GND
4
ACK
Clock
DI/O
>
nMOS
DATA
REGISTER
PIN CONFIGURATION
8-Pin DIP, SOIC, TSSOP
PIN DESCRIPTIONS
A0-A2
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SDA
SCL
WP
Vcc
GND
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses and
data into and out of the device. The SDA pin is an open drain
output and can be wire-Or'ed with other open drain or open
collector outputs. The SDA bus
requires
a pullup resistor to
Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C01B/02B uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.
WP
WP is the Write Protect pin. If the WP pin is tied to V
CC
on the
EEPROM, the entire array becomes Write Protected (Read
only). When WP is tied to GND or left floating normal read/
write operations are allowed to the device.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00B
11/15/04
IS24C01B
IS24C02B
Stop Condition
ISSI
®
DEVICE OPERATION
IS24C01B/02B features serial communication and supports
a bi-directional 2-wire bus transmission protocol called I
2
C
TM
.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24C01B/02B is the Slave device on the bus.
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The
IS24C01B/02B
contains a reset function in case
the 2-wire bus transmission is accidentally interrupted
(eg. a power loss), or needs to be terminated mid-
stream. The reset is caused when the Master device
creates a Start condition. To do this, it may be
necessary for the Master device to monitor the SDA
line while cycling the SCL up to nine times. (For each
clock signal transition to High, the Master checks for a
High level on SDA.)
The Bus Protocol:
– Data transfer may be initiated only when the bus is not busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a Start
or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of the
High period of the clock signal. The data on the SDA line may
be changed during the Low period of the clock signal. There
is one clock pulse per bit of data. Each data transfer is
initiated with a Start condition and terminated with a Stop
condition.
Standby Mode
Power consumption is reduced in standby mode. The
IS24C01B/02B will enter standby mode: a) At Power-up,
and remain in it until SCL or SDA toggles; b) Following
the Stop signal if a no write operation is initiated; or c)
Following any internal write operation.
Start Condition
The Start condition precedes all commands to the device and
is defined as a High to Low transition of SDA when SCL is High.
The EEPROM monitors the SDA and SCL lines and will not
respond until the Start condition is met.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00B
11/15/04
3
IS24C01B
IS24C02B
WRITE OPERATION
Byte Write
ISSI
®
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave device address
are fixed as 1010 for the IS24C01B/02B.
The next three bits of the Slave address are specific for
each of the EEPROM. The bit values enable access to
multiple memory blocks or multiple devices.
The IS24C01B/02B uses the three bits A0, A1, and A2 in
a comparison with the hard-wired input values on the A0,
A1, and A2 pins. Up to eight units may share the 2-wire
bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C02B) will respond with ACK on the SDA line. The
Slave will pull down the SDA on the ninth clock cycle,
signaling that it received the eight bits of data. The selected
EEPROM then prepares for a Read or Write operation by
monitoring the bus.
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the IS24C01B/02B. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The IS24C01B/02B acknowledges once
more and the Master generates the Stop condition, at
which time the device begins its internal programming
cycle. While this internal cycle is in progress, the device
will not respond to any request from the Master device.
Page Write
The IS24C01B/02B is capable of 8-byte Page-Write
operation. A Page-Write is initiated in the same manner as
a Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 7 more bytes. After the receipt of
each data word, the EEPROM responds immediately with an
ACK on SDA line, and the three lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
If a byte address is incremented from the last byte of a
page, it returns to the first byte of that page. If the Master
device should transmit more than 8 bytes prior to issuing the
Stop condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 8 bytes
are received and the Stop condition has been sent by the
Master, the internal programming cycle begins. At this point,
all received data is written to the IS24C01B/02B in a single
Write cycle. All inputs are disabled until completion of the
internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of
the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C01B/02B initiates the internal Write cycle. ACK polling
can be initiated immediately. This involves issuing the
Start condition followed by the Slave address for a Write
operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C01B/02B
has completed the Write operation, an ACK will be returned
and the host can then proceed with the next Read or Write
operation.
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00B
11/15/04
IS24C01B
IS24C02B
Random Address Read
ISSI
®
READ OPERATION
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
is set to “1”. There are three Read operation options:
current address read, random address read and sequential
read.
Current Address Read
The IS24C01B/02B contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the EEPROM
receives the Slave Addressing Byte with a Read operation
(R/W bit set to “1”), it will respond an ACK and transmit the
8-bit data byte stored at address location n+1. The Master
should not acknowledge the transfer but should generate
a Stop condition so the IS24C01B/02B discontinues
transmission. If 'n' is the last byte of the memory, the data
from location '0' will be transmitted. (Refer to Figure 8.
Current Address Read Diagram.)
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read.
After the IS24C01B/02B acknowledges the byte address,
the Master device resends the Start condition and the
Slave address, this time with the R/W bit set to one. The
EEPROM then responds with its ACK and sends the data
requested. The Master device does not send an ACK but
will generate a Stop condition. (Refer to Figure 9. Random
Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C01B/02B sends the initial byte sequence, the Master
device now responds with an ACK, indicating it requires
additional data from the IS24C01B/02B. The EEPROM
continues to output data for each ACK received. The
Master device terminates the sequential Read operation
by pulling SDA High (no ACK) indicating the last data word
to be read, followed by a Stop condition.
The data output is sequential, with the data from address
n followed by the data from address n+1,n+2 ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundary of 127 or 255 (depending on the device) is
reached, the address counter “rolls over” to address 0, and
the device continues to output data. (Refer to Figure 10.
Sequential Read Diagram).
Integrated Silicon Solution, Inc. — www.issi.com —
SynQor推出超小的病人全接触型400W医疗电源模块，该电源模块的封装为3×5×1.44，功率密度高达18.3W/立方英寸，转换效率达91%。 SynQor通过推出首款专门针对医疗应用而研制的AC/DC电源模块，使得公司的多元化战略持续成功地延伸至新的医疗领域。ACuQor模块系列实现了在3×5×1.44有限尺寸上提供400W的有用功率。SynQor可以提供48V，36V or 24V的...[详细]
随着阅读器与标签价格的降低和全球市场的扩大，射频标识 RFID(以下简称RFID)的应用与日俱增。标签既可由阅读器供电(无源标签)，也可以由标签的板上电源供电(半有源标签和有源标签)。由于亚微型无源 CMOS 标签的成本降低，库存和其他应用迅速增加。一些评估表明，随着无源标签的价格持续下降，几乎每一个售出产品的内部都将有一个 RFID 标签。由于无源 RFID 标签的重要性及其独特的工程实现...[详细]
Microchip MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
