ExpressLane
PEX 8624-AA, AB,
and
BB
24-Lane/6-Port PCI Express Gen 2 Switch
Data Book
Version 1.3
June 2012
Website
www.plxtech.com
Technical Support
www.plxtech.com/support
Phone 800 759-3735
408 774-9060
FAX 408 774-2169
Copyright © 2012 by PLX Technology, Inc. All Rights Reserved – Version 1.3
June, 2012
Data Book
PLX Technology, Inc.
Revision History
Version
1.0
1.1
Date
February, 2009
September, 2009
Description of Changes
Production release, Silicon Revision BB.
Support for pre-Production Silicon Revisions AA and AB is also included.
Production update, Silicon Revision BB.
Applied miscellaneous corrections, changes, and enhancements throughout data book.
Production update, Silicon Revision BB.
Added support for Industrial temperature.
Updated PEX 8624 part ordering information.
Applied miscellaneous corrections, changes, and enhancements throughout data book.
Production update, Silicon Revision BB.
Corrected the JTAG IDCODE version number.
Updated the thermal matrix table.
Updated the ordering part number.
Applied miscellaneous corrections, changes, and enhancements throughout data book.
1.2
October, 2010
1.3
June, 2012
Copyright Information
Copyright © 2009 – 2012 PLX Technology, Inc. All Rights Reserved. The information in this document
is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any
form or by any means or used to make any derivative work (such as translation, transformation, or
adaptation) without written permission from PLX Technology.
PLX Technology provides this documentation without warranty, term or condition of any kind, either
express or implied, including, but not limited to, express and implied warranties of merchantability,
fitness for a particular purpose, and non-infringement. While the information contained herein is
believed to be accurate, such information is preliminary, and no representations or warranties of
accuracy or completeness are made. In no event will PLX Technology be liable for damages arising
directly or indirectly from any use of or reliance upon the information contained in this document.
PLX Technology may make improvements or changes in the product(s) and/or the program(s) described
in this documentation at any time.
PLX Technology retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX Technology assumes no
liability whatsoever, including infringement of any patent or copyright, for sale and use
of PLX Technology products.
PLX Technology and the PLX logo are registered trademarks and Dual Cast, ExpressLane,
performancePAK,
Read Pacing, and
visionPAK
are trademarks of PLX Technology, Inc.
PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG).
EUI-64 is a trademark of The Institute of Electrical and Electronics Engineers, Inc. (IEEE).
Tri-State is a registered trademark of Texas Instruments, Inc.
All product names are trademarks, registered trademarks, or service marks of their respective owners.
Document Number: 8624-AA/AB/BB-SIL-DB-P1-1.3
ii
ExpressLane PEX 8624-AA, AB, and BB 24-Lane/6-Port PCI Express Gen 2 Switch Data Book, Version 1.3
Copyright © 2012 by PLX Technology, Inc. All Rights Reserved
June, 2012
Preface
Preface
The information in this data book is subject to change without notice. This PLX data book to be updated
periodically as new information is made available.
Audience
This data book provides functional details of PLX Technology’s ExpressLane PEX 8624-AA, AB, and
BB 24-Lane/6-Port PCI Express Gen 2 Switch, for hardware designers and software/firmware
engineers. The information provided pertains to all Silicon Revisions (AA, AB, and BB), unless
specified otherwise.
Supplemental Documentation
This data book assumes that the reader is familiar with the following documents:
•
PLX Technology, Inc. (PLX),
www.plxtech.com
The
PLX PEX 8624 Toolbox
includes this data book and other supporting documentation,
such as
errata, and design and application notes.
•
The Institute of Electrical and Electronics Engineers, Inc. (IEEE),
www.ieee.org
– IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan
Architecture
– IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan
Architecture
– IEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions
– IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan
Architecture Extensions
•
NXP Semiconductors,
ics.nxp.com
–
The I2C-Bus Specification, Version 2.1
•
PCI Special Interest Group (PCI-SIG),
www.pcisig.com
– PCI Local Bus Specification, Revision 3.0
– PCI Bus Power Management Interface Specification, Revision 1.2
– PCI to PCI Bridge Architecture Specification, Revision 1.2
– PCI Express Base Specification, Revision 1.1
– PCI Express Base Specification, Revision 2.0
– PCI Express Base Specification, Revision 2.0 Errata
– PCI Express Card Electromechanical Specification, Revision 2.0
– PCI Express Mini Card Electromechanical Specification, Revision 1.1
–
PCI Express Architecture PCI Express Jitter and BER White Paper, Revision 1.0
•
Personal Computer Memory Card International Association (PCMCIA),
www.pcmcia.org
– ExpressCard Standard Release 1.0
•
PXI Systems Alliance (PXI),
www.pxisa.org
– PXI-5 PXI Express Hardware Specification, Revision 1.0
ExpressLane PEX 8624-AA, AB, and BB 24-Lane/6-Port PCI Express Gen 2 Switch Data Book, Version 1.3
Copyright © 2012 by PLX Technology, Inc. All Rights Reserved
iii
Supplemental Documentation
PLX Technology, Inc.
Note:
In this data book, shortened titles are associated with the previously listed documents.
The following table lists these abbreviations.
Abbreviation
PCI r3.0
PCI Power Mgmt. r1.2
PCI-to-PCI Bridge r1.2
PCI Express Base r1.1
PCI Express Base r2.0
PCI ExpressCard CEM r2.0
PCI ExpressCard Mini CEM r1.1
IEEE Standard 1149.1-1990
IEEE Standard 1149.6-2003
I
2
C Bus v2.1
I2C Bus v2.1
a
Document
PCI Local Bus Specification, Revision 3.0
PCI Bus Power Management Interface Specification, Revision 1.2
PCI to PCI Bridge Architecture Specification, Revision 1.2
PCI Express Base Specification, Revision 1.1
PCI Express Base Specification, Revision 2.0
PCI Express Card Electromechanical Specification, Revision 2.0
PCI Express Mini Card Electromechanical Specification, Revision 1.1
IEEE Standard Test Access Port and Boundary-Scan Architecture
IEEE Standard Test Access Port and Boundary-Scan Architecture
Extensions
The I
2
C-Bus Specification, Version 2.1
a.
Due to formatting limitations, the specification name may appear without the superscripted
“2” in its title.
iv
ExpressLane PEX 8624-AA, AB, and BB 24-Lane/6-Port PCI Express Gen 2 Switch Data Book, Version 1.3
Copyright © 2012 by PLX Technology, Inc. All Rights Reserved
June, 2012
Terms and Abbreviations
Terms and Abbreviations
The following table lists common terms and abbreviations used in this data book. Terms and
abbreviations defined in the
PCI Express Base r2.0
are not included in this table.
Terms and
Abbreviations
8b/10b
ACK
AMCAM
ARI
BAR
BER
BusNoCAM
CAM
CDR
CRC
CSR
DLL
DMA
Downstream Station
ECC
ECRC
EIOS
EP
Field
FC
GPIO
GT/s
INCH
InitFC
IOCAM
JTAG
Lane
LCRC
Link Interface
Definitions
Data-encoding scheme used on data transferred across a Link that is operating at either
Gen 1 or Gen 2 Link speed (2.5 or 5.0 GT/s, respectively).
Acknowledge Control Packet. Control packet used by a destination to acknowledge
data packet receipt. Signal that acknowledges signal receipt.
Address-mapping CAM that determines a memory Request route. Contains mirror copies
of the PCI-to-PCI bridge
Memory Base
and
Memory Limit
registers in the PEX 8624.
Alternative Routing-ID Interpretation.
Base Address register.
Bit error rate.
Bus Number-mapping CAM that determines the Completion route. Contains mirror
copies of the PCI-to-PCI bridge
Secondary Bus Number
and
Subordinate Bus Number
registers in the PEX 8624.
Content-Addressable Memory.
Clock Data Recovery.
Cyclic Redundancy Check.
Configuration Space register.
Data Link Layer.
Direct Memory Access.
Station that contains only downstream Ports.
Error-Correcting Code.
End-to-end Cyclic Redundancy Check.
Electrical Idle Ordered-Set.
Endpoint.
Multiple register bits that are combined for a single function.
Flow Control.
General-Purpose Input/Output.
Giga-Transfers per second.
Ingress Credit Handler.
Initialization Flow Control.
I/O-mapping CAM that determines an I/O Request route. Contains mirror copies of the
PCI-to-PCI bridge
I/O Base
and
I/O Limit
registers in the PEX 8624.
Joint Test Action Group.
Bidirectional pair of differential PCI Express I/O signals.
Link Cyclic Redundancy Check.
Primary side of the NT Port, connects to external device pins. The secondary side
of the NT Port is referred to as the
NT Port Virtual Interface,
and connects to the
internal virtual PCI Express interface.
ExpressLane PEX 8624-AA, AB, and BB 24-Lane/6-Port PCI Express Gen 2 Switch Data Book, Version 1.3
Copyright © 2012 by PLX Technology, Inc. All Rights Reserved
v