UL6264A
Low Voltage 8K x 8 SRAM
Features
F
Packages:
Description
F
8192 x 8 bit static CMOS RAM
F
250 and 500 ns Access Times
F
Common data inputs and data
outputs
F
Three-state outputs
F
Typ. operating supply current:
F
F
F
F
F
F
F
F
F
PDIP28(600 mil)
SOP28 (330 mil)
250 ns: 12 mA
500 ns: 7 mA
Standby current < 5
µA
Standby current at 25
°C
and 3.3 V: typ. 50 nA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 3.3 V
Operating temperature ranges
0 to 70
°C
-25 to 85
°C
-40 to 85
°C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
The UL6264A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L) or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G the data
inputs, or outputs, are active. In the
active state E1 = L and E2 = H,
each address change leads to a
new Read or Write cycle. In a Read
cycle, the data outputs are activa-
ted by the falling edge of G, after-
wards the data word read will be
available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The data outputs have no
preferred state. If the memory is
driven by CMOS levels in the active
state, and if there is no change of
the address, data input and control
signals W or G, the operating cur-
rent (at I
O
= 0 mA) drops to the
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V.
With the exception of E2, all inputs
consist of NOR gates, so that no
pull-up/pull-down
resistors
are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
If the circuit is inactivated by E2 = L,
the standby current (TTL) drops to
100
µA
typ.
Pin Configuration
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
PDIP
22
SOP
21
20
19
18
17
16
15
Top View
December 12, 1997
315
UL6264A
Block Diagram
A4
A5
A6
A7
A8
A9
A11
A12
A0
A1
A2
A3
A10
Row Address
Inputs
Row Decoder
Memory Cell
Array
256 Rows x
256 Columns
Column Address
Inputs
Column Decoder
DQ0
Common Data-I/O
Sense Amplifier/
Write Control Logic
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
E2
1
E1
V
CC
V
SS
W
G
Truth Table
Operating Mode
Standby/not
selected
Internal Read
Read
Write
* H or L
E1
*
H
L
L
L
E2
L
*
H
H
H
W
*
*
H
H
L
G
*
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating
Temperature
Storage Temperature
C-Type
G-Type
K-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
Min.
-0.3
-0.3
-0.3
Max.
7
V
CC
+ 0.5
V
CC
+ 0.5
1
Unit
V
V
V
W
°C
°C
°C
°C
December 12, 1997
0
-25
-40
-55
316
70
85
85
125
T
stg
UL6264A
Symbol
Switching Characteristics
Alt.
Time to Output in Low-Z
G LOW to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold Time from End of Write
Output Hold Time from Address
Change
E1 HIGH or E2 LOW to Output in
High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
LZ
t
OLZ
t
WC
t
RC
t
ACE
t
OE
t
AA
t
WP
t
CW
t
AS
t
CW
t
WP
t
DS
t
DH
t
AH
t
OH
t
HZCE
t
HZWE
t
HZOE
IEC
t
t(QX)
t
tG(QX)
t
cW
t
cR
t
a(E)
t
a(G)
t
a(A)
t
w(W)
t
w(E)
t
su(A)
t
su(E)
t
su(W)
t
su(D)
t
h(D)
t
h(A)
t
v(A)
t
dis(E)
t
dis(W)
t
dis(G)
25
20
10
250
250
50
20
10
500
500
25
50
ns
ns
ns
ns
Min.
Max.
Unit
-
-
-
120
180
0
180
120
80
0
0
20
0
0
0
-
-
-
150
210
0
210
150
100
0
0
20
0
0
0
250
100
250
500
100
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
60
40
60
60
40
ns
ns
ns
Data Retention Mode E1-Controlled
V
CC
3.0 V
V
CC(DR)
≥
2 V
2.0 V
t
DR
0V
Data Retention
t
rec
2.0 V
E1
0V
Data Retention Mode E2-Controlled
V
CC
V
CC(DR)
≥
2 V
t
DR
0.8 V
Data Retention
V
E2(DR)
≤
0.2 V
t
rec
0.8 V
3.0 V
E2
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
t
DR
:
t
rec
:
min 0 ns
min t
cR
318
December 12, 1997
UL6264A
Test Configuration for Functional Check
Input level according to the
relevant test measurement
ment of all 8 output pins
Simultaneous Measure-
V
IH
V
IL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
V
CC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
3.3 V
960
Q Q
V
O
Q
V
O
E1
E2
W
G
100 pF
V
SS
510
5 pF
L1
L1: For dynamic measurement except t
dis
-times
L2: For t
dis
-times
L2
Capacitance
Input Capacitance
Output Capacitance
Conditions
V
CC
= 3.3 V
V
I
= V
SS
f
T
a
= 1 MHz
= 25
°C
Symbol
C
I
C
O
Min.
Max.
8
10
Unit
pF
pF
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
UL6264A
Type
Package
D = PDIP
S = SOP
Operating Temperature Range
C =
0 to 70 °C
G = -25 to 85 °C
K = -40 to 85 °C
Access Time
25 = 250 ns
50 = 500 ns
D
G
25
The date of manufacture is given by the 4 last digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
December 12, 1997
319
FPGA/CPLD
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