TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
Features
100-pin plastic quad flat pack (QFP), surface-
mount package
IEEE 488.1-compatible transceivers on chip
Fast data transfers
– Up to 1.5 Mbytes/s using interlocked
IEEE 488.1 handshake
– Up to 8 Mbytes/s using HS488
™
Two 8-bit 16-deep FIFOs buffer data
between GPIB and CPU
With exception of Controller, performs all
IEEE 488 interface functions
– SH1, AH1, T5 or TE5, L3 or LE3,
SR1, RL1, PP1 or PP2, DC1, DT1,
and C0
Meets all IEEE 488.2 requirements
– Bus line monitoring
– Preferred implementation of
requesting service
– Not sending messages when there are
no Listeners
Software compatible with
Turbo488 /NAT4882
™
ASICs
Reduces software overhead
– Does not lose a data byte if ATN is
asserted while transmitting data
– Static interrupts status bits that do
not clear when read
™
NEW!
– Automatically transmits END or
performs RFD holdoff on last byte
of DMA transfer
– Interrupts when handshake is
complete on last byte of a DMA
transfer
– Has 32-bit counter for large,
uninterrupted data transfers
Programmable timer interrupt for
general-purpose timing use
Complete in-system functional testing
with internal loop-back mode
ISA bus glue logic on chip
Direct memory access (DMA)
Device status indicator pins
– My Address, Talk Addressed, Listen
Addressed, REM, DCAS, TRIG
Automatically processes IEEE 488
commands and reads undefined
commands
Handles 6 primary and secondary
addressing modes
Automatic EOS and/or NL message
detection
Programmable data transfer rate –
TTL-compatible CMOS device
Description
The TNT4882 provides a single-chip IEEE 488.2 Talker/Listener
interface to the general-purpose interface bus (GPIB). The
TNT4882 combines the circuitry of the NAT4882 IEEE 488.2
application-specific integrated circuit (ASIC), Turbo488
performance-enhancing ASIC, and GPIB transceivers to create a
single-chip IEEE 488.2 interface. Because the TNT4882 contains
the NAT4882 register set, which in turn has the NEC µPD7210
and TI TMS 9914A register sets, developers using any of these
chips can easily port existing code directly to the TNT4882,
thereby significantly reducing software development time. Also,
with just a few modifications, you can implement all the
improved features of the IEEE 488.2 standard. The TNT4882 is
ideal for use in all IEEE 488 instrument designs because of its
small size, surface-mount ability, and performance
enhancements that include HS488, a new high-speed mode for
GPIB transfers.
Architecture, Modes
The TNT4882 integrates the circuitry of the Turbo488, NAT4882,
and IEEE 488.1- compatible transceivers. The TNT4882 circuitry
logically interconnects these three components in one of two
ways – “one-chip mode” (see Figure 1) or “two-chip mode”
(see Figure 2).
The TNT4882 powers up in two-chip mode, which exactly
duplicates the Turbo488/NAT4882 chipset for software
compatibility. During I/O accesses in two-chip mode, the CPU
accesses the Turbo488 and passes all accesses within a certain
address range to the NAT4882. The Turbo488 also manages
transfers between its internal first-in first-out buffers (FIFOs) and
the NAT4882, arbitrating between these data transfers and any
I/O accesses of the NAT4882 by the CPU. Accesses to the
NAT4882 registers take longer than Turbo488 accesses because
all accesses to the NAT4882 registers must go through the
Turbo488 and its arbiter.
To achieve higher data transfer rates, you can switch the
TNT4882 to one-chip mode in software. In one-chip mode, the
first-in first-out (FIFO) buffer connects directly to the GPIB
transceivers and the CPU accesses all registers directly. You can
access NAT4882 registers in the same amount of time as
Turbo488 registers because accesses to these registers do not go
through the Turbo488.
The NAT4882 portion of the TNT4882 can emulate either the
NEC µPD7210 or the TI TMS9914A GPIB controller chips. The
state of one of the TNT4882 input pins determines the chip
emulation mode on power up, but you can switch the chip
emulation mode back and forth between 7210 and 9914
modes through software.
HS488 Overview
The HS488 high-speed mode for GPIB transfers increases the
maximum data transfer rate of devices on a GPIB network up to
8 Mbytes/s. The TNT4882 completely and transparently handles
the HS488 protocol without additional circuitry, a method that is
a superset of the IEEE 488 standard. Thus, you can mix existing
GPIB devices with HS488 devices without changing your
application programs. The TNT4882 can implement high-speed
data transfers automatically. Maximum data transfer rates
obtainable using HS488 depend on the host architecture and
system configuration.
340570D-01
030599
TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
The register map of the NAT4882 portion of the TNT4882
changes to emulate either the 7210 or the 9914, but the
Turbo488 registers are identical in both chip emulation modes.
You cannot use one-chip mode with the 9914 emulation mode.
Because the Turbo488 was designed to interface to the 7210
and not the 9914, the software can rearrange the register map
of the 9914 mode NAT4882 registers so that the 9914 mode
Command/Data Out Register and Data In Register and the
Auxiliary Command Register appear at the same addresses as the
corresponding 7210 mode registers. The Turbo488 can then
perform DMA transfers with the NAT4882 in 9914 mode.
The TNT4882 has two different pin configurations – Generic
(see Figure 3) and ISA (see Figure 4). The TNT4882 determines
which configuration to use by the location of the power (VDD)
and ground pins. The Generic pin configuration provides a
simple interface to any CPU. Using the ISA pin configuration, you
can connect the TNT4882 directly to an ISA (IBM PC AT) bus
without any external glue logic or data transceivers. You can also
use the ISA pin configuration TNT4882 with an 8-bit (PC/XT) bus.
You may want to use the ISA version for interfaces other than an
ISA bus to take advantage of the built-in 5-bit address decoder.
You can use two-chip mode, one-chip mode, 7210 mode, and
9914 mode identically with either pin configuration.
TNT4882 Block Diagrams
FIFOs
Configuration
and
Status Registers
IEEE 488
Interface
Functions
IEEE 488
Transceivers
Timer
HS488
Interface
Functions
Interrupt Control
Figure 1. TNT4882 One-Chip Mode
Turbo488 Circuitry
FIFOs
NAT4882
Interface
Circuitry
NAT4882 Circuitry
Read/
Write
Control
GPIB
Data
Registers
Read/
Write
Control
Byte
Counter
Transfer
State
Machine
Configuration
and
Status Registers
IEEE 488
Interface
Functions
Local GPIB Signals
ISA
Interface
Logic
IEEE 488
Transceivers
IEEE 488 Bus
ISA
Interface
Logic
Read/
Write
Control
Byte
Counter
IEEE 488 Monitor
GPIB
Configuration
and
Status Registers
Timer
Interrupt Control
Interrupt Control
IEEE 488 Monitor
Figure 2. TNT4882 Two-Chip Mode
2
National Instruments
Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com
TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
Generic Pin Configuration
RESETN
LADCS
GND
GND
DIO8N
RENN
DIO5N
IFCN
GND
DIO6N
SRQN
GND
DIO7N
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NDACN
NRFDN
GND
DAVN
EOIN
GND
VDD
DIO4N
DIO3N
GND
DIO2N
DIO1N
GND
VDD
XTAL0
XTAL1
GND
KEYCLKN
KEYDQ
KEYRSTN
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
DATA7
DATA6
GND
DATA5
DATA4
GND
DATA3
DATA2
DATA1
GND
VDD
DATA0
RDY1
GND
VDD
GND
INTR
DACKN
DRQ
BURST_RDN
VDD
GND
WRN
RDN
BBUSN
GND
VDD
GND
VDD
GND
GND
CSN
GND
MODE
NC
DCAS
42
41
40
39
38
37
36
35
34
33
32
ABUS_OEN
TADCS
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
BBUS_OEN
DATA15
DATA14
DATA13
DATA12
DATA11
GND
DATA10
DATA9
DATA8
GND
VDD
GND
ABUSN
ADDR0
ADDR1
FIFO_RDY
CPUACC
TRIG
VDD
GND
PAGED
GND
REM
SWAPN
ADDR2
ADDR3
ADDR4
Figure 3. TNT4882 Generic Pin Configuration
Generic Pin Description
All pins with names that end in ‘N’ are active low; all others are active high. All input (I) and bidirectional (I/O) pins have an internal pull-up
resistor between 50 kΩ and 150 kΩ.
Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more
information.
Pin No.(s)
1
2,3,5,6,7,9,10,11
14
19-15
20
21
22
23
26
28
29
30
31
Name(s)
BBUS_OEN
DATA15-8
ABUSN
ADDR4-0
ABUS_OEN
TADCS
CPUACC
TRIG
PAGED
REM
SWAPN
FIFO_RDY
BURST_RDN
Type
O
I/O
I
I
O
O
O
O
I
O
I
O
I
Description
Asserts when DATA7-0 (B bus) is enabled for output
Upper 8 bits of bidirectional three-state data bus for transfer of commands, data, and status
between TNT4882 and CPU – also known as the A bus
Enables register accesses through the A bus (DATA15-8) – DATA15 is the most significant bit
Determines which register to access during a read or write operation
Asserts when DATA15-8 (A bus) is enabled for output
Asserts when the TNT4882 is an active or addressed IEEE 488 Talker (TADS, TACS, or SPAS)
Asserts in two-chip mode during a NAT4882 register I/O access
Asserts when in DTAS or when the auxiliary trigger software command is issued
Asserting this pin pages in the page-in registers in the 7210 mode
Asserts when the TNT4882 is in a remote state (REMS or RWLS)
Rearranges the order of the registers when asserted and in 9914 mode
Asserts when the FIFO is ready for burst access
When asserted, places the TNT4882 in a burst read mode, in which the first word in the
FIFO is always driven on the TNT4882 data bus – words are removed from the FIFOs at
each rising edge of RDN – see reference manual for details
Asserts to request a DMA transfer cycle
Enables FIFO accesses during a DMA transfer cycle
Asserts when one or more of the unmasked interrupt conditions becomes true
Asserts during an I/O access to indicate that the read data is available or that the write
data has been latched – asserts immediately on an access to Turbo488 registers or in
one-chip mode
Lower eight bits of bidirectional three-state data bus for transfer of commands, data, and
status between TNT4882 and CPU – also known as the B bus – DATA7 is the most significant bit
32
33
34
38
DRQ
DACKN
INTR
RDY1
ATNN
TNT4882
Generic Pin Configuration
O
I
O
O
50,49,47,46,
44,43,42,39
DATA7-0
I/O
Table continued on page 4
National Instruments
Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com
3
TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
Table continued from page 3
Pin No.(s)
51
52
53
55
62
63
64
66
67
71,74,77
,80,88,
89,91,92
70,73,76,79,
81,82,84,85
95
96
98
99
100
4,8,13,25,27,35,37
41,45,48,54,56,57,
59,61,65,68,72,75,
78,83,86,90,93,97
12,24,36,40,58,
60,69,87,94
Name(s)
DCAS
NC
MODE
CSN
BBUSN
RDN
WRN
LADCS
RESETN
DIO8-1N
RENN, ATNN, SRQN,
IFCN, NDACN, NRFDN,
DAVN, EOIN
XTAL0
XTAL1
KEYCLKN
KEYDQ
KEYRSTN
GND
Type
O
O
I
I
I
I
I
O
I
I/O
I/O
Description
Asserts when the device clear state machine is in DCAS
Leave this pin unconnected
Determines whether the TNT4882 powers up in 7210 or 9914 emulation mode –
High = 7210 mode, Low = 9914 mode
Chip Select enables I/O transfers between the CPU and the TNT4882
Enables register accesses through the B bus (DATA7-0)
Enables the contents of the registers selected by ADDR 4:0 and CSN or the FIFOs to
appear on the data bus selected by ABUSN and BBUSN
Latches data on the bus selected by ABUSN and BBUSN into an internal TNT4882 register
on the trailing (rising) edge of WRN
Asserts when the TNT4882 is addressed as a Listener
Holds the TNT4882 in its idle state
8-bit bidirectional IEEE 488 data bus
IEEE 488 control signals
O
I
O
I/O
O
_
Output of crystal circuit – use only for driving a quartz crystal
Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal
Strobes data to or from a DS1204 electronic key
Transmits serial data between the TNT4882 and a DS1204 key
Resets a DS1204 key
Ground pins – 0 V
VDD
_
Power pins – +5 V (±5%)
GND
DIO8N
DIO5N
IFCN
GND
DIO6N
GND
DIO7N
SRQN
RESET
IOCS16N
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NDACN
NRFDN
GND
DAVN
EOIN
GND
VDD
DIO4N
DIO3N
GND
DIO2N
DIO1N
GND
VDD
XTAL0
XTAL1
GND
KEYCLKN
KEYDQ
KEYRSTN
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DATA7
DATA6
GND
DATA5
DATA4
GND
DATA3
DATA2
DATA1
GND
VDD
DATA0
IOCHRDY
AEN_N
VDD
GND
INTR
DACKN
DRQ
ADDR9
TNT4882
ISA Pin Configuration
VDD
GND
GND
D15_8_OEN
NC
SW6
BHEN_N
GND
ADDR5
GND
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
SW7
VDD
ADDR6
D7_0_OEN
DATA15
DATA14
GND
DATA13
DATA12
Figure 4. TNT4882 ISA Pin Configuration
4
National Instruments
Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com
DATA11
GND
DATA10
DATA9
DATA8
VDD
GND
ADDR7
ADDR8
IOWN
IORN
SENSE_8_16N
GND
VDD
VDD
VDD
GND
VDD
SW5
NC
MODE
SW9
SW8
ISA Pin Configuration
RENN
ATNN
TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
ISA Pin Description
All input (I) and bidirectional (I/O) pins have an internal pull-up resistor between 50 kΩ and 150 kΩ. Pins with names that end in “N” are
active low signals – all others are active high. Open-collector outputs are type “OC.”
Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more
information.
Pin No.(s)
1
2,3,5,6,7,9,10,11
Name(s)
D7_0_OEN
DATA15-8
Type
O
I/O
Description
Asserts when DATA7-0 bus is enabled for output – may be left unconnected
Upper eight bits of bidirectional three-state data bus for transfer of commands,
data, and status between TNT4882 and CPU – can connect directly to the AT bus –
DATA15 is the most significant bit
Enables access to upper eight bits of data bus when asserted
Determines which register will be accessed during an I/O access
Determines if an I/O address is within the range occupied by the TNT4882 –
the chip is selected and an I/O access occurs when ADDR9-5 match SW9-5 and
AEN_N is asserted
Asserts when DATA15:8 bus is enabled for output – may be left unconnected
Leave unconnected
Determines the base address of the TNT4882
Asserts to request a DMA transfer cycle
Enables FIFO accesses during a DMA transfer cycle
Asserts when one or more of the unmasked interrupt conditions becomes true
Enables I/O accesses to the TNT4882
When the TNT4882 is not accessed, this open-collector signal is not driven, and a
pull-up resistor on the system board keeps it pulled high – at the start of some
TNT4882 accesses, the TNT4882 may drive it low, then pull it high again during the
cycle to indicate that the TNT4882 is ready for the CPU to end that cycle
Lower eight bits of bidirectional three-state data bus for transfer of commands, data,
and status between TNT4882 and CPU – can connect directly to the AT bus – DATA7
is the most significant bit
Forces the TNT4882 to 7210 (high) or 9914 (low) emulation mode on a hardware
reset – may be left unconnected
Pull this pin low to tell the TNT4882 that it is connected to a 16-bit bus – leave it
unconnected if the TNT4882 is connected to an 8-bit bus
Drives the contents of the register selected by ADDR4-0 on the data bus when the
TNT4882 is selected
The value on the data bus is latched into the register selected by ADDR4-0 on the
rising edge of IOWN when you select the TNT4882
Driven low during an access to the upper data bus
Causes a hardware reset and holds the TNT4882 in its idle state while asserted
8-bit bidirectional IEEE 488 data bus
IEEE 488 control signals
14
19-15
31,30,29,28,26
BHEN_N
ADDR4-0
ADDR9-5
I
I
I
20
21,54
52,51,23,22,55
32
33
34
37
38
D15_8_OEN
NC
SW9-5
DRQ
DACKN
INTR
AEN_N
IOCHRDY
O
O
I
O
I
O
I
OC
50,49,47,46,44,
43,42,39
53
62
63
64
66
67
71,74,77,80,88,
89,91,92
70,73,76,79,81,
82,84,85
95
96
98
99
100
4,8,13,25,27,35,41,
45,48,57,61,65,68,72,
75,78,83,86,90,93,97
12,24,36,40,56,58,
59,60,69,87
,94
DATA7-0
I/O
MODE
SENSE_8_16N
IORN
IOWN
IOCS16N
RESET
DIO8-1N
RENN, ATNN, SRQN,
IFCN, NDACN, NRFDN,
DAVN, EOIN
XTAL0
XTAL1
KEYCLKN
KEYDQ
KEYRSTN
GND
I
I
I
I
OC
I
I/O
I/O
O
I
O
I/O
O
–
Output of crystal circuit – use only for driving a quartz crystal
Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal
Strobes data to or from the DS1204 electronic key
Transmits serial data between the TNT4882 and a DS1204 key
Resets a DS1204 key
Ground pins – 0 V
VDD
–
Power pins – +5 V (±5%)
National Instruments
Phone: (512) 794-0100 • Fax: (512) 683-9300 • info@natinst.com • www.natinst.com
5
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