TECHNICAL DATA
IN74LV574
Octal D-type flip-flop;
positive edge-trigger (3-State)
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for oriented
applications. A clock (CP) and an output enable (OE) input are common to
all flip-flops. The eight flip-flops will store the state of their individual D-
inputs that meet the set-up and hold times requirements on the LOW-to-
HIGH CP transition. When OE is LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the state of
the flip-flops.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
•
Supply voltage range: 1.0 to 5.5 V
•
Low input current: 1.0
µА;
0.1
µА
at
Т
= 25
°С
•
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
IN74LV574N
Plastic DIP
IN74LV574DW
SOIC
T
A
= -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
PIN 20=V
CC
PIN 10 = GND
L
L
L
H
L,H,
X
Clock
D
H
L
X
X
Output
Q
H
L
no
change
Z
H= high level
L = low level
X = don’t care
Z = high impedance
1
IN74LV574
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
DC supply voltage
Input diode current
Output diode current
Output source or sink current
V
CC
current
GND current
Power dissipation per package:
Plastic DIP *
4
SO *
4
Storage Temperature
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm
(SO Package) from Case for 4 Seconds
Parameter
Value
-0.5 to +7.0
±20
±50
±35
±70
±70
750
500
-65 to +150
260
°C
°C
Unit
V
mA
mA
mA
mA
mA
mW
Tstg
T
L
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: : - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
0 V
≤
V
CC
≤
2.0 V
2.0 V
≤
V
CC
≤
2.7 V
2.7 V
≤
V
CC
≤
3.6 V
3.6 V
≤
V
CC
≤
5.5 V
Parameter
Min
1.0
0
0
-40
0
0
0
0
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
IN74LV574
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
Symbol
Paramete
r
HIGH
level input
voltage
conditions
V
CC
V
25°C
min
V
IH
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
V
I
= V
IH
or
V
IL
I
O
= -100
µА
1.2
2.0
2.7
3.0
3.6
4.5
5.5
3.0
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.05
1.85
2.55
2.85
3.45
4.35
5.35
2.48
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
Guaranteed Limit
-40°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.05
1.85
2.55
2.85
3.45
4.35
5.35
2.48
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
85°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
2.40
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
125°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
2.20
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
V
Unit
V
IL
LOW level
output
voltage
V
V
OH
HIGH
level
output
voltage
V
V
I
= V
IH
or
V
IL
I
O
= -8 mА
V
I
= V
IH
or
V
IL
I
O
= -16 mА
V
OL
LOW level V
I
= V
IH
or
output
V
IL
voltage
I
O
= 100
µА
V
4.5
3.70
-
3.70
-
3.60
-
3.50
-
V
1.2
2.0
2.7
3.0
3.6
4.5
5.5
3.0
-
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.33
-
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.33
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.40
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.50
V
V
I
= V
IH
or
V
IL
I
O
= 8 mА
V
I
= V
IH
or
V
IL
I
O
= 16 mА
I
I
I
CC
Input
current
Supply
current
V
I
= V
CC
or
0V
V
I
=V
CC
or
0V
I
O
= 0
µА
V
4.5
-
0.40
-
0.40
-
0.55
-
0.65
V
5.5
5.5
-
-
±0.1
8.0
-
-
±0.1
8.0
-
-
±1.0
20
-
-
±1.0
160
µА
µА
3
IN74LV574
I
CC1
Additional V
I
= V
CC
–
supply
0.6V
current per
input
Three state 3-state output
leakage
V
I
(11) = V
IH
V
O
=V
CC
or
current
0V
2.7
3.6
-
0.2
-
0.2
-
0.5
0.85
mA
I
OZ
5.5
-
±0.5
-
±0.5
-
±5
-
±10
µА
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
Symbol
Parameter
conditions
V
I
= 0 V or V
1
Figures 1,3
V
CC
V
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
5.5
5.5
min
t
PHL,
t
PLH
Propagation delay , Clock
to Q
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
160
26
20
16
14
160
31
23
20
17
140
26
20
16
14
7.0*
50*
Guaranteed Limit
-40°C to 25°C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85°C
min
max
170
34
25
20
17
170
39
29
24
20
160
34
25
20
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
125°C
min
max
200
43
31
25
21
200
48
36
29
24
180
43
31
25
21
-
-
ns
Unit
t
PHZ,
t
PLZ
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
ns
t
PZH,
t
PZL
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
ns
C
I
C
PD
* T = 25
o
C
Input capacitance
Power dissipation
V
I
= 0 V or V
CC
capacitance (per flip-flop)
pF
pF
TEST POINT
DEVICE
UNDER
TEST
TEST POINT
1k
C
L
*
OUTPUT
C
L
*
DEVICE
UNDER
TEST
OUTPUT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND when
testing t
PHZ
and t
PZH
* Includes all probe and jig capacitance
Figure 1. Test Circuit
* Includes all probe and jig capacitance
Figure 2. Test Circuit
4
IN74LV574
TIMING REQUIREMENTS
C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
Symbol
t
w
Parameter
conditions
V
CC
V
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
1.2
2.0
2.7
3.0
4.5
min
Pulse Width, Clock (high) V
I
= 0 V or V
1
Figures 1,3
120
29
21
17
15
40
19
14
11
9
5
5
5
5
-
-
-
-
-
max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
17
21
27
31
Guaranteed Limit
-40°C to 25°C
85°C
min
34
25
20
max
-
-
-
125°C
min
41
30
24
max
ns
-
-
-
ns
22
16
13
5
5
5
5
-
-
-
-
-
-
-
-
-
-
15
19
24
26
19
15
5
5
5
5
-
-
-
-
-
-
-
-
-
-
12
16
20
ns
Unit
t
su
Setup Time, Data to Clock V
I
= 0 V or V
1
Figures 1,5
t
h
Hold Time, Clock to Data V
I
= 0 V or V
1
Figures 1,5
f
c
Clock Frequency
V
I
= 0 V or V
1
Figures 1,3
MHz
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Figure 3. Switching Waveforms
5
FPGA/CPLD
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